From: Ferruh Yigit <ferruh.yigit@intel.com>
To: Hyong Youb Kim <hyonkim@cisco.com>
Cc: dev@dpdk.org, John Daley <johndale@cisco.com>
Subject: Re: [dpdk-dev] [PATCH] net/enic: use 64B completion queue entries if available
Date: Mon, 18 Jan 2021 15:05:04 +0000 [thread overview]
Message-ID: <30c5fcbc-0d9f-0767-b31b-b038fd27466e@intel.com> (raw)
In-Reply-To: <20210107140154.23499-1-hyonkim@cisco.com>
On 1/7/2021 2:01 PM, Hyong Youb Kim wrote:
> Latest VIC adapters support 64B CQ (completion queue) entries as well
> as 16B entries available on all VIC models. 64B entries can greatly
> reduce cache contention (CPU stall cycles) between DMA writes (Rx
> packet descriptors) and polling CPU. The effect is very noticeable on
> Intel platforms with DDIO. As most UCS servers are based on Intel
> platforms, enable and use 64B CQ entries by default, if
> available. Also, add devarg 'cq64' so the user can explicitly disable
> 64B CQ.
>
> Signed-off-by: Hyong Youb Kim <hyonkim@cisco.com>
> Reviewed-by: John Daley <johndale@cisco.com>
Applied to dpdk-next-net/main, thanks.
prev parent reply other threads:[~2021-01-18 15:05 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-07 14:01 Hyong Youb Kim
2021-01-18 15:05 ` Ferruh Yigit [this message]
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