From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B7597A0A03; Mon, 18 Jan 2021 16:05:32 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8C29F140F1A; Mon, 18 Jan 2021 16:05:32 +0100 (CET) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id 99494140F13 for ; Mon, 18 Jan 2021 16:05:31 +0100 (CET) IronPort-SDR: +RJX3usSbH4fAMvLFosyeh0f9gmfJCARp/veUM0ZrBJzgSwV9CicvQY0YJydHtk5z6FwqpPxd9 Zqy7ntHn2hmg== X-IronPort-AV: E=McAfee;i="6000,8403,9867"; a="263620076" X-IronPort-AV: E=Sophos;i="5.79,356,1602572400"; d="scan'208";a="263620076" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jan 2021 07:05:09 -0800 IronPort-SDR: WA6tCCS+8PiWwT4vy5VsphedfmCZOFY6o7D7AkRBorwoBQWL5h1FiUoK/isASpAwcKq16Wn/io R+0vG3IFnH3Q== X-IronPort-AV: E=Sophos;i="5.79,356,1602572400"; d="scan'208";a="383600267" Received: from fyigit-mobl1.ger.corp.intel.com (HELO [10.213.241.24]) ([10.213.241.24]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jan 2021 07:05:07 -0800 To: Hyong Youb Kim Cc: dev@dpdk.org, John Daley References: <20210107140154.23499-1-hyonkim@cisco.com> From: Ferruh Yigit Message-ID: <30c5fcbc-0d9f-0767-b31b-b038fd27466e@intel.com> Date: Mon, 18 Jan 2021 15:05:04 +0000 MIME-Version: 1.0 In-Reply-To: <20210107140154.23499-1-hyonkim@cisco.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Subject: Re: [dpdk-dev] [PATCH] net/enic: use 64B completion queue entries if available X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 1/7/2021 2:01 PM, Hyong Youb Kim wrote: > Latest VIC adapters support 64B CQ (completion queue) entries as well > as 16B entries available on all VIC models. 64B entries can greatly > reduce cache contention (CPU stall cycles) between DMA writes (Rx > packet descriptors) and polling CPU. The effect is very noticeable on > Intel platforms with DDIO. As most UCS servers are based on Intel > platforms, enable and use 64B CQ entries by default, if > available. Also, add devarg 'cq64' so the user can explicitly disable > 64B CQ. > > Signed-off-by: Hyong Youb Kim > Reviewed-by: John Daley Applied to dpdk-next-net/main, thanks.