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Thu, 14 Sep 2017 08:05:25 +0000 From: Yongseok Koh To: Shahaf Shuler CC: =?iso-8859-1?Q?N=E9lio_Laranjeiro?= , "Adrien Mazarguil" , "dev@dpdk.org" , "stable@dpdk.org" Thread-Topic: [PATCH v4 4/4] net/mlx5: enforce Tx num of segments limitation Thread-Index: AQHTLH4q2joZKfhfkESKXPmeYUxnWKKyxSoAgAEVDoCAAC08Ug== Date: Thu, 14 Sep 2017 08:05:25 +0000 Message-ID: <31018994-DB44-486B-B880-579804057124@mellanox.com> References: <7b6d42c0c5e1a04f8483b6546ea0b1db8fb7ceee.1505133966.git.shahafs@mellanox.com> <20170913195154.GA4263@yongseok-MBP.local>, In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=yskoh@mellanox.com; x-originating-ip: [73.222.116.174] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; VI1PR0501MB2735; 6:N6htqBlNQN443fyAtvlLj78zPgqXRbkfieF3n+j0AM/gKcR0ZNEg51t2sAjSDlYn3E3UsUFt/NZIqlMl1448WyqutOaRPvBZYoYljjZnoS0RTFn6V7pE4zxtD1dvLW0bUTzkZ2OhLp0qDAIKTjT4FoPexlTY3sPLqmI4oPScCEQhTcdpF7p1IZQnHQe/NS70SH2ETWYv0ds/tntRtwX3vKvk5offlL9UsGM165MIW21kfZbfYiAaee9FIpYpsCS7goDMD8+xUPVcgv50Wrbsm65zsOxzjEdL+YD3mGPplWR73zQjiCiS0trAQMwWJNVlp9Fiq54t1C39FCB2WeUd4Q==; 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DIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR0501MB2735; H:VI1PR0501MB2045.eurprd05.prod.outlook.com; FPR:; SPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Sep 2017 08:05:25.5716 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0501MB2735 Subject: Re: [dpdk-dev] [PATCH v4 4/4] net/mlx5: enforce Tx num of segments limitation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Sep 2017 08:05:27 -0000 Thanks! Yongseok > On Sep 13, 2017, at 10:23 PM, Shahaf Shuler wrote: >=20 > Hi Yongseok, >=20 > Wednesday, September 13, 2017 10:52 PM, Yongseok Koh: >>>=20 >>> +/* Maximum number of DS in WQE. */ >>> +#define MLX5_MAX_DS 63 >> How about make it consistent with MLX5_MPW_DSEG_MAX by naming >> MLX5_DSEG_MAX? >=20 > It doesn't have the same meaning.=20 >=20 > The MLX5_MPW_DSEG_MAX is to limit the number of mbuf segments (buf->nb_se= gs) for multi packet wqe. The inline part is taken into account different= ly.=20 > The MLX_MAX_DS is to limit the number data segments (i.e. MLX5_WQE_DWORD_= SIZE) that could be set into a WQE. This includes everything (inline, ctrl = seg, eth seg, pointers). > For the regular Tx burst there are many options for different inline size= s which impact on the max number of mbuf segments possible. I should've been clearer. I just suggested a small change from DS to DSEG a= s I thought DS and DSEG are same. But if it just comes from the field name = in WQE Ctrl segment, MLX5_WQE_DS_MAX or MLX5_WQE_CTRL_DS_MAX could be good.= I hoped it could be a little more explanatory. I'm not good at naming, wil= l defer to you. :-) > BTW - am still not sure why we have the MLX5_MPW_DSEG_MAX limitation. I don't know either. We should discuss it with chip design. Thanks Yongseok =