From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 38A76A0547; Mon, 19 Apr 2021 10:47:49 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A423D40683; Mon, 19 Apr 2021 10:47:48 +0200 (CEST) Received: from new3-smtp.messagingengine.com (new3-smtp.messagingengine.com [66.111.4.229]) by mails.dpdk.org (Postfix) with ESMTP id 4450E40040 for ; Mon, 19 Apr 2021 10:47:47 +0200 (CEST) Received: from compute2.internal (compute2.nyi.internal [10.202.2.42]) by mailnew.nyi.internal (Postfix) with ESMTP id 6426F58108A; Mon, 19 Apr 2021 04:47:46 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute2.internal (MEProxy); Mon, 19 Apr 2021 04:47:46 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s=fm1; bh= J9C+jKLBbl1Fau1CGmkdz+FXoHF2W4fqdE9yV9wCOwk=; b=IBJzkCYxieU9/Yyj TnR8QGpXHH2TuPv1ul4FRy1MMDRw95tvOou7YZeMoeJGI0rHI/zdlyMfDHYHKV4Z xl4u58eYzjnAjV8t05ZHjnMALAqQw4YBiUW9oa4IZwAjI8QfiJhQSRy3yWCmNNHG 8/es/F4CyyLqsCSyWqj40T4y/A6CYRj6fyID/G77uVwaPS1QZBV8VlQEeweb+u66 IKpPE7dXAECvLAiKISKQmhHa9OiyJIhsOIwAKAe/MsixOYcPk4Dg4oBuAOSu7gI1 cKts+J0pMluKMpMmx6dAbZ07EUT9kimh9u/973C6pknSA/+sdz3cL9i3cOmi6/+X IqlSdA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm2; bh=J9C+jKLBbl1Fau1CGmkdz+FXoHF2W4fqdE9yV9wCO wk=; b=g8PuecdhrQwzK2qlBB5NM+DDax/eWgyb7nsbMspAwDXB6382924DKfsOj j07gydFIdXaFio/hjinkBowmnvwz7vo075Jd/VfWCp6kK1qN7fKxP7BI+FY2CWBz JIlplKBkITEb4syWUIho2DtRu2Q4FDUjVq1rhivAx2hiTd/r6anm/8s6HPi/zG+T FfEdNvcOOhJXPsk1m+wzC1XeQmUIGNIeiYrAHwCjCBeRCG7sJCJilBfIWI5NlOs1 wv6Dr3oRS++Dwraja5q06SShQZjswRA5u+rRgej/dL0PkTO2VojZ2SpvSfZOX55B 5cP2Nj0XxS+L+R411TLwH2rUqOg9Q== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeduledrvddtgedgtdekucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkfgjfhgggfgtsehtufertddttddvnecuhfhrohhmpefvhhhomhgr shcuofhonhhjrghlohhnuceothhhohhmrghssehmohhnjhgrlhhonhdrnhgvtheqnecugg ftrfgrthhtvghrnhepudeggfdvfeduffdtfeeglefghfeukefgfffhueejtdetuedtjeeu ieeivdffgeehnecukfhppeejjedrudefgedrvddtfedrudekgeenucevlhhushhtvghruf hiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpehthhhomhgrshesmhhonhhjrghl ohhnrdhnvght X-ME-Proxy: Received: from xps.localnet (184.203.134.77.rev.sfr.net [77.134.203.184]) by mail.messagingengine.com (Postfix) with ESMTPA id 150A2240054; Mon, 19 Apr 2021 04:47:43 -0400 (EDT) From: Thomas Monjalon To: Gregory Etelson Cc: orika@nvidia.com, ajit.khaparde@broadcom.com, andrew.rybchenko@oktetlabs.ru, dev@dpdk.org, ferruh.yigit@intel.com, jerinj@marvell.com, jerinjacobk@gmail.com, olivier.matz@6wind.com, viacheslavo@nvidia.com, matan@nvidia.com, rasland@nvidia.com Date: Mon, 19 Apr 2021 10:47:42 +0200 Message-ID: <3158315.YsgzKm6jbH@thomas> In-Reply-To: <20210419082908.8805-2-getelson@nvidia.com> References: <20210419082908.8805-1-getelson@nvidia.com> <20210419082908.8805-2-getelson@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Subject: Re: [dpdk-dev] [PATCH v7 1/2] ethdev: add packet integrity checks X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" 19/04/2021 10:29, Gregory Etelson: > +Item: ``PACKET_INTEGRITY_CHECKS`` > +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ > + > +Matches packet integrity. > +For some devices application needs to enable integration checks in HW > +before using this item. > + > +- ``level``: the encapsulation level that should be checked. level 0 means the > + default PMD mode (Can be inner most / outermost). value of 1 means outermost > + and higher value means inner header. See also RSS level. Would be nicer to make sub-list for levels. Please start sentences with a capital letter. > +- ``packet_ok``: All HW packet integrity checks have passed based on the max > + layer of the packet. "based on the max layer" is not clear. Do you mean all layers? > +- ``l2_ok``: all layer 2 HW integrity checks passed. > +- ``l3_ok``: all layer 3 HW integrity checks passed. > +- ``l4_ok``: all layer 4 HW integrity checks passed. > +- ``l2_crc_ok``: layer 2 crc check passed. s/crc/CRC/ > +- ``ipv4_csum_ok``: ipv4 checksum check passed. s/ipv4/IPv4/ > +- ``l4_csum_ok``: layer 4 checksum check passed. > +- ``l3_len_ok``: the layer 3 len is smaller than the frame len. s/len/length/ > --- a/doc/guides/rel_notes/release_21_05.rst > +++ b/doc/guides/rel_notes/release_21_05.rst > +* **Added packet integrity match to flow rules.** > + > + * Added ``RTE_FLOW_ITEM_TYPE_INTEGRITY`` flow item. > + * Added ``rte_flow_item_integrity`` data structure. It should be moved with other ethdev changes. > + > * **Added support for Marvell CN10K SoC drivers.** > > Added Marvell CN10K SoC support. Marvell CN10K SoC are based on Octeon 10 > --- a/lib/librte_ethdev/rte_flow.h > +++ b/lib/librte_ethdev/rte_flow.h > + /** > + * [META] > + * > + * Matches on packet integrity. > + * For some devices application needs to enable integration checks in HW > + * before using this item. > + * > + * See struct rte_flow_item_integrity. Better to use @see syntax. > + */ > + RTE_FLOW_ITEM_TYPE_INTEGRITY, > }; > +struct rte_flow_item_integrity { > + /**< Tunnel encapsulation level the item should apply to. > + * @see rte_flow_action_rss > + */ > + uint32_t level; missing RTE_STD_C11 here for anonymous union. > + union { > + __extension__ > + struct { > + /**< The packet is valid after passing all HW checks. */ > + uint64_t packet_ok:1; > + /**< L2 layer is valid after passing all HW checks. */ > + uint64_t l2_ok:1; > + /**< L3 layer is valid after passing all HW checks. */ > + uint64_t l3_ok:1; > + /**< L4 layer is valid after passing all HW checks. */ > + uint64_t l4_ok:1; > + /**< L2 layer CRC is valid. */ > + uint64_t l2_crc_ok:1; > + /**< IPv4 layer checksum is valid. */ > + uint64_t ipv4_csum_ok:1; > + /**< L4 layer checksum is valid. */ > + uint64_t l4_csum_ok:1; > + /**< The l3 length is smaller than the frame length. */ > + uint64_t l3_len_ok:1; > + uint64_t reserved:56; > + }; > + uint64_t value; > + }; > +};