From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3F554A0542; Wed, 15 Jul 2020 19:24:33 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 8283E4C8A; Wed, 15 Jul 2020 19:24:32 +0200 (CEST) Received: from new2-smtp.messagingengine.com (new2-smtp.messagingengine.com [66.111.4.224]) by dpdk.org (Postfix) with ESMTP id DE4AC2B9A for ; Wed, 15 Jul 2020 19:24:30 +0200 (CEST) Received: from compute7.internal (compute7.nyi.internal [10.202.2.47]) by mailnew.nyi.internal (Postfix) with ESMTP id 745115811AD; Wed, 15 Jul 2020 13:24:30 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute7.internal (MEProxy); Wed, 15 Jul 2020 13:24:30 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s=fm1; bh= HSYxUeEDCNTAuezcF7Y6J+wEL0E+B1unk9SmdBfKkFc=; b=hKbgLXe+6xZF3nBS gzpI9463IXJS0cR/Xuj9O1Nj7Qtz+TqiNhOV9QEPfGx9De0ij+PFfOOO6SkVHABO gjBMWjfEDoj02tDVuq27J7BzPVyh1kKHPKV4gT1ctDTbzurp9rwDZJCyx4Jh0IDC LjKSgshp+rToPvqIEX3l9ejPeYXGMs8UhFUgTzgbiCwW0cNMHf9ObYp+cS9NDi5B 7Iiz6RBncFILDglM5S8V+bmhFs1r31BfujpgvgttxELrdJUjh0eOPQ99Bk2JpBRo PRcI93Hbv/VSK073iW9jB7nfaENbQ6cG3X8M4cnAQRiNkuIpIPL8mFrOcNgFT+fl qeJPWw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm3; bh=HSYxUeEDCNTAuezcF7Y6J+wEL0E+B1unk9SmdBfKk Fc=; b=qiVcc9dzUOKU0CbcEytLdcCFjYqe0tlToSCNHw9rpAmx9jRQhzclObJmp XXu8Rts7RXXvAk9PfKfTkCYNnK26Ohi2F9F0jsEJx/MoEu3zJ/Tz7ZnpD0ni06Bg F7klaeIdMh6OHmDu3Xty1L+1j/qSXO5t/iiO4Csgd/a6l1cy4uegIjJ49rFl1Zy0 SWeNHKQbxGQ45iQ5XmWMfB09ak3XzB1awqRlqbBgVFbr2DPXHg0L0r9dydyqjKD7 tNqZXv//h5kZYZBAqS6m9sXwQ8rbHSedafsJf+bk/PY5wq8kPKKiejVFyXyvXg3g iGTY+2a1+TUE5C2wpOnYKZCZs2s5Q== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeduiedrfedvgdduudekucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkfgjfhgggfgtsehtufertddttddvnecuhfhrohhmpefvhhhomhgr shcuofhonhhjrghlohhnuceothhhohhmrghssehmohhnjhgrlhhonhdrnhgvtheqnecugg ftrfgrthhtvghrnhepudeggfdvfeduffdtfeeglefghfeukefgfffhueejtdetuedtjeeu ieeivdffgeehnecukfhppeejjedrudefgedrvddtfedrudekgeenucevlhhushhtvghruf hiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpehthhhomhgrshesmhhonhhjrghl ohhnrdhnvght X-ME-Proxy: Received: from xps.localnet (184.203.134.77.rev.sfr.net [77.134.203.184]) by mail.messagingengine.com (Postfix) with ESMTPA id 178D8328005A; Wed, 15 Jul 2020 13:24:26 -0400 (EDT) From: Thomas Monjalon To: Ori Kam Cc: jerinj@marvell.com, xiang.w.wang@intel.com, matan@mellanox.com, viacheslavo@mellanox.com, Shahaf Shuler , dev@dpdk.org, guyk@marvell.com, dev@dpdk.org, pbhagavatula@marvell.com, hemant.agrawal@nxp.com, opher@mellanox.com, alexr@mellanox.com, dovrat@marvell.com, pkapoor@marvell.com, nipun.gupta@nxp.com, bruce.richardson@intel.com, yang.a.hong@intel.com, harry.chang@intel.com, gu.jian1@zte.com.cn, shanjiangh@chinatelecom.cn, zhangy.yun@chinatelecom.cn, lixingfu@huachentel.com, wushuai@inspur.com, yuyingxia@yxlink.com, fanchenggang@sunyainfo.com, davidfgao@tencent.com, liuzhong1@chinaunicom.cn, zhaoyong11@huawei.com, oc@yunify.com, jim@netgate.com, hongjun.ni@intel.com, deri@ntop.org, fc@napatech.com, arthur.su@lionic.com, rasland@mellanox.com, Yuval Avnery Date: Wed, 15 Jul 2020 19:24:23 +0200 Message-ID: <3439450.e4May6JWUA@thomas> In-Reply-To: <1594587541-110442-5-git-send-email-orika@mellanox.com> References: <1593941027-86651-1-git-send-email-orika@mellanox.com> <1594587541-110442-1-git-send-email-orika@mellanox.com> <1594587541-110442-5-git-send-email-orika@mellanox.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Subject: Re: [dpdk-dev] [PATCH v2 04/20] common/mlx5: add mlx5 regex command structs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" 12/07/2020 22:58, Ori Kam: > From: Yuval Avnery > > Add regex commands structs to support regex. Addind data stuctures without any use of it is meaningless. We can probably squash a lot of commits. > Signed-off-by: Yuval Avnery > Acked-by: Viacheslav Ovsiienko > > --- > --- a/drivers/common/mlx5/mlx5_prm.h > +++ b/drivers/common/mlx5/mlx5_prm.h > @@ -795,7 +795,7 @@ enum { > MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, > MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, > MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, > - MLX5_CMD_SET_REGEX_PARAM = 0xb04, > + MLX5_CMD_SET_REGEX_PARAMS = 0xb04, Should be part of previous patch. > MLX5_CMD_QUERY_REGEX_PARAMS = 0xb05, > MLX5_CMD_SET_REGEX_REGISTERS = 0xb06, > MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07, > @@ -2526,6 +2526,93 @@ struct mlx5_ifc_query_qp_in_bits { > u8 reserved_at_60[0x20]; > }; > > +struct regexp_params_field_select_bits { > + u8 reserved_at_0[0x1e]; > + u8 stop_engine[0x1]; > + u8 db_umem_id[0x1]; > +}; > + > +struct mlx5_ifc_regexp_params_bits { > + u8 reserved_at_0[0x1f]; > + u8 stop_engine[0x1]; > + u8 db_umem_id[0x20]; > + u8 db_umem_offset[0x40]; > + u8 reserved_at_80[0x100]; > +}; > + > +struct mlx5_ifc_set_regexp_params_in_bits { > + u8 opcode[0x10]; > + u8 uid[0x10]; > + u8 reserved_at_20[0x10]; > + u8 op_mod[0x10]; > + u8 reserved_at_40[0x18]; > + u8 engine_id[0x8]; > + struct regexp_params_field_select_bits field_select; > + struct mlx5_ifc_regexp_params_bits regexp_params; > +}; > + > +struct mlx5_ifc_set_regexp_params_out_bits { > + u8 status[0x8]; > + u8 reserved_at_8[0x18]; > + u8 syndrome[0x20]; > + u8 reserved_at_18[0x40]; > +}; > + > +struct mlx5_ifc_query_regexp_params_in_bits { > + u8 opcode[0x10]; > + u8 uid[0x10]; > + u8 reserved_at_20[0x10]; > + u8 op_mod[0x10]; > + u8 reserved_at_40[0x18]; > + u8 engine_id[0x8]; > + u8 reserved[0x20]; > +}; > + > +struct mlx5_ifc_query_regexp_params_out_bits { > + u8 status[0x8]; > + u8 reserved_at_8[0x18]; > + u8 syndrome[0x20]; > + u8 reserved[0x40]; > + struct mlx5_ifc_regexp_params_bits regexp_params; > +}; > + > +struct mlx5_ifc_set_regexp_register_in_bits { > + u8 opcode[0x10]; > + u8 uid[0x10]; > + u8 reserved_at_20[0x10]; > + u8 op_mod[0x10]; > + u8 reserved_at_40[0x18]; > + u8 engine_id[0x8]; > + u8 register_address[0x20]; > + u8 register_data[0x20]; > + u8 reserved[0x40]; > +}; > + > +struct mlx5_ifc_set_regexp_register_out_bits { > + u8 status[0x8]; > + u8 reserved_at_8[0x18]; > + u8 syndrome[0x20]; > + u8 reserved[0x40]; > +}; > + > +struct mlx5_ifc_query_regexp_register_in_bits { > + u8 opcode[0x10]; > + u8 uid[0x10]; > + u8 reserved_at_20[0x10]; > + u8 op_mod[0x10]; > + u8 reserved_at_40[0x18]; > + u8 engine_id[0x8]; > + u8 register_address[0x20]; > +}; > + > +struct mlx5_ifc_query_regexp_register_out_bits { > + u8 status[0x8]; > + u8 reserved_at_8[0x18]; > + u8 syndrome[0x20]; > + u8 reserved[0x20]; > + u8 register_data[0x20]; > +};