From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 8B47E2BBE for ; Fri, 15 Sep 2017 15:17:40 +0200 (CEST) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Sep 2017 06:17:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,396,1500966000"; d="scan'208";a="900586121" Received: from irsmsx151.ger.corp.intel.com ([163.33.192.59]) by FMSMGA003.fm.intel.com with ESMTP; 15 Sep 2017 06:17:37 -0700 Received: from irsmsx101.ger.corp.intel.com ([169.254.1.22]) by IRSMSX151.ger.corp.intel.com ([169.254.4.108]) with mapi id 14.03.0319.002; Fri, 15 Sep 2017 14:17:37 +0100 From: "Trahe, Fiona" To: "Burakov, Anatoly" , "dev@dpdk.org" CC: "Griffin, John" , "Jain, Deepak K" , "De Lara Guarch, Pablo" Thread-Topic: [PATCH v2 3/3] crypto/qat: enable TX tail writes coalescing Thread-Index: AQHTK6nu66yGwjH43EKl1LllWeOuEKK18nBQ Date: Fri, 15 Sep 2017 13:17:37 +0000 Message-ID: <348A99DA5F5B7549AA880327E580B43589294A3B@IRSMSX101.ger.corp.intel.com> References: <8aada4555a65d6ceb8b581f7909020a487ee9f3b.1505142402.git.anatoly.burakov@intel.com> In-Reply-To: <8aada4555a65d6ceb8b581f7909020a487ee9f3b.1505142402.git.anatoly.burakov@intel.com> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZjUwYmIzZDktNWU4NS00NjRkLTk1OGEtMjQ4MTM3MTAxMDAzIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE2LjUuOS4zIiwiVHJ1c3RlZExhYmVsSGFzaCI6ImR0MVRhYUVhbFNwUzZ5ekp0UnJxQUJLTkh5ek8wbW45MU9YV1JnMkw1eGc9In0= x-ctpclassification: CTP_IC dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [163.33.239.180] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2 3/3] crypto/qat: enable TX tail writes coalescing X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Sep 2017 13:17:40 -0000 > -----Original Message----- > From: Burakov, Anatoly > Sent: Tuesday, September 12, 2017 10:31 AM > To: dev@dpdk.org > Cc: Trahe, Fiona ; Griffin, John ; Jain, Deepak K > ; De Lara Guarch, Pablo > Subject: [PATCH v2 3/3] crypto/qat: enable TX tail writes coalescing >=20 > Don't write CSR tail until we processed enough TX descriptors. >=20 > To avoid crypto operations sitting in the TX ring indefinitely, > the "force write" threshold is used: > - on TX, no tail write coalescing will occur if number of inflights > is below force write threshold > - on RX, check if we have a number of crypto ops enqueued that is > below force write threshold that are not yet submitted to > processing. >=20 > Signed-off-by: Anatoly Burakov Acked-by: Fiona Trahe