From: "Trahe, Fiona" <fiona.trahe@intel.com>
To: "Ananyev, Konstantin" <konstantin.ananyev@intel.com>,
"dev@dpdk.org" <dev@dpdk.org>
Cc: "akhil.goyal@nxp.com" <akhil.goyal@nxp.com>,
"umesh.kartha@caviumnetworks.com"
<umesh.kartha@caviumnetworks.com>,
"De Lara Guarch, Pablo" <pablo.de.lara.guarch@intel.com>,
"shally.verma@caviumnetworks.com"
<shally.verma@caviumnetworks.com>,
"Ananyev, Konstantin" <konstantin.ananyev@intel.com>,
"Trahe, Fiona" <fiona.trahe@intel.com>
Subject: Re: [dpdk-dev] [PATCH] cryptodev: fix restore crypto op alignment and layout
Date: Fri, 8 Mar 2019 12:59:21 +0000 [thread overview]
Message-ID: <348A99DA5F5B7549AA880327E580B4358970F211@IRSMSX101.ger.corp.intel.com> (raw)
In-Reply-To: <1551967994-8112-1-git-send-email-konstantin.ananyev@intel.com>
> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Konstantin Ananyev
> Sent: Thursday, March 7, 2019 2:13 PM
> To: dev@dpdk.org
> Cc: akhil.goyal@nxp.com; umesh.kartha@caviumnetworks.com; De Lara Guarch, Pablo
> <pablo.de.lara.guarch@intel.com>; shally.verma@caviumnetworks.com; Ananyev, Konstantin
> <konstantin.ananyev@intel.com>
> Subject: [dpdk-dev] [PATCH] cryptodev: fix restore crypto op alignment and layout
>
> in 18.08 new cache-aligned structure rte_crypto_asym_op was introduced.
> As it also was included into rte_crypto_op, it caused implicit change
> in rte_crypto_op layout and alignment: now rte_crypto_op is cahce-line
> aligned has a hole of 40/104 bytes between phys_addr and sym/asym op.
> It looks like unintended ABI breakage, plus such change can cause
> negative performance effects:
> - now status and sym[0].m_src lies on different cache-lines, so
> post-process code would need extra cache-line read.
> - new alignment causes grow of the space requirements and cache-line
> reads/updates for structures that contain rte_crypto_op inside.
> As there seems no actual need to have rte_crypto_asym_op cache-line
> aligned, and rte_crypto_asym_op is not intended to be used on it's own -
> the simplest fix is just to remove cache-line alignment for it.
> As the immediate positive effect: on IA ipsec-secgw performance increased
> by 5-10% (depending on the crypto-dev and algo used).
> My guess that on machines with 128B cache-line and lookaside-protocol
> capable crypto devices the impact will be even more noticeable.
>
> Fixes: 26008aaed14c ("cryptodev: add asymmetric xform and op definitions")
>
> Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
next prev parent reply other threads:[~2019-03-08 12:59 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-07 14:13 Konstantin Ananyev
2019-03-08 12:59 ` Trahe, Fiona [this message]
2019-03-12 12:04 ` Shally Verma
2019-03-19 13:33 ` Akhil Goyal
2019-03-19 13:33 ` Akhil Goyal
2019-03-19 14:00 ` Akhil Goyal
2019-03-19 14:00 ` Akhil Goyal
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