From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CC3E6A0548; Fri, 24 Sep 2021 11:11:00 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B3A3B4122D; Fri, 24 Sep 2021 11:11:00 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 2DEA340142 for ; Fri, 24 Sep 2021 11:10:58 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10116"; a="211274712" X-IronPort-AV: E=Sophos;i="5.85,319,1624345200"; d="scan'208";a="211274712" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Sep 2021 02:10:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,319,1624345200"; d="scan'208";a="436937034" Received: from fmsmsx603.amr.corp.intel.com ([10.18.126.83]) by orsmga003.jf.intel.com with ESMTP; 24 Sep 2021 02:10:58 -0700 Received: from shsmsx605.ccr.corp.intel.com (10.109.6.215) by fmsmsx603.amr.corp.intel.com (10.18.126.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Fri, 24 Sep 2021 02:10:57 -0700 Received: from shsmsx601.ccr.corp.intel.com (10.109.6.141) by SHSMSX605.ccr.corp.intel.com (10.109.6.215) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Fri, 24 Sep 2021 17:10:50 +0800 Received: from shsmsx601.ccr.corp.intel.com ([10.109.6.141]) by SHSMSX601.ccr.corp.intel.com ([10.109.6.141]) with mapi id 15.01.2242.012; Fri, 24 Sep 2021 17:10:50 +0800 From: "Zhang, Qi Z" To: "Zhang, AlvinX" CC: "dev@dpdk.org" Thread-Topic: [PATCH v3] net/ice: add support for low Rx latency Thread-Index: AQHXsSIjoI4zm5oy1U+6nq++To4jequy5aLQ Date: Fri, 24 Sep 2021 09:10:50 +0000 Message-ID: <3850ecc7f08b41fb91d479add4f6acb3@intel.com> References: <20210918025923.5112-1-alvinx.zhang@intel.com> <20210924085653.17080-1-alvinx.zhang@intel.com> In-Reply-To: <20210924085653.17080-1-alvinx.zhang@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.6.200.16 dlp-product: dlpe-windows x-originating-ip: [10.239.127.36] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v3] net/ice: add support for low Rx latency X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Zhang, AlvinX > Sent: Friday, September 24, 2021 4:57 PM > To: Zhang, Qi Z > Cc: dev@dpdk.org; Zhang, AlvinX > Subject: [PATCH v3] net/ice: add support for low Rx latency >=20 > This patch adds a devarg parameter to enable/disable low Rx latency. >=20 > Signed-off-by: Alvin Zhang > --- >=20 > v3: rebase to dpdk-next-net-intel > --- > doc/guides/nics/ice.rst | 12 ++++++++++++ > drivers/net/ice/ice_ethdev.c | 26 +++++++++++++++++++++++--- > drivers/net/ice/ice_ethdev.h | 1 + > 3 files changed, 36 insertions(+), 3 deletions(-) >=20 > diff --git a/doc/guides/nics/ice.rst b/doc/guides/nics/ice.rst index > ebe2cbc..355f192 100644 > --- a/doc/guides/nics/ice.rst > +++ b/doc/guides/nics/ice.rst > @@ -227,6 +227,18 @@ Runtime Config Options >=20 > -a af:00.0,pps_out=3D'[pin:0]' >=20 > +- ``Low Rx latency`` (default ``0``) > + > + vRAN workloads require low latency DPDK interface for the front haul > + interface connection to Radio. By specifying ``1`` for parameter > + ``rx-low-latency``, each completed Rx descriptor can be written > + immediately to host memory and the Rx interrupt latency can be reduced > to 2us:: > + > + -a 0000:88:00.0,rx-low-latency=3D1 > + > + As a trade-off, this configuration may cause the packet processing > + performance degradation due to the PCI bandwidth limitation. > + > Driver compilation and testing > ------------------------------ >=20 > diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c = index > e24a3b6..9edf811 100644 > --- a/drivers/net/ice/ice_ethdev.c > +++ b/drivers/net/ice/ice_ethdev.c > @@ -30,6 +30,7 @@ > #define ICE_PROTO_XTR_ARG "proto_xtr" > #define ICE_HW_DEBUG_MASK_ARG "hw_debug_mask" > #define ICE_ONE_PPS_OUT_ARG "pps_out" > +#define ICE_RX_LOW_LATENCY "rx-low-latency" Should it has ARG suffix to align the naming rule? >=20 > static const char * const ice_valid_args[] =3D { > ICE_SAFE_MODE_SUPPORT_ARG, > @@ -37,6 +38,7 @@ > ICE_PROTO_XTR_ARG, > ICE_HW_DEBUG_MASK_ARG, > ICE_ONE_PPS_OUT_ARG, > + ICE_RX_LOW_LATENCY, > NULL > }; >=20 > @@ -1956,6 +1958,9 @@ static int ice_parse_devargs(struct rte_eth_dev > *dev) > if (ret) > goto bail; >=20 > + ret =3D rte_kvargs_process(kvlist, ICE_RX_LOW_LATENCY, > + &parse_bool, &ad->devargs.rx_low_latency); > + > bail: > rte_kvargs_free(kvlist); > return ret; > @@ -3272,8 +3277,9 @@ static int ice_init_rss(struct ice_pf *pf) { > struct ice_hw *hw =3D ICE_VSI_TO_HW(vsi); > uint32_t val, val_tx; > - int i; > + int rx_low_latency, i; >=20 > + rx_low_latency =3D vsi->adapter->devargs.rx_low_latency; > for (i =3D 0; i < nb_queue; i++) { > /*do actual bind*/ > val =3D (msix_vect & QINT_RQCTL_MSIX_INDX_M) | @@ -3283,8 > +3289,21 @@ static int ice_init_rss(struct ice_pf *pf) >=20 > PMD_DRV_LOG(INFO, "queue %d is binding to vect %d", > base_queue + i, msix_vect); > + > /* set ITR0 value */ > - ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2); > + if (rx_low_latency) { > + /** > + * Empirical configuration for optimal real time > + * latency reduced interrupt throttling to 2us > + */ > + ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x1); > + ICE_WRITE_REG(hw, QRX_ITR(base_queue + i), > + QRX_ITR_NO_EXPR_M); > + } else { > + ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2); > + ICE_WRITE_REG(hw, QRX_ITR(base_queue + i), 0); > + } > + > ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val); > ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx); > } > @@ -5497,7 +5516,8 @@ static int ice_xstats_get_names(__rte_unused struct > rte_eth_dev *dev, > ICE_HW_DEBUG_MASK_ARG "=3D0xXXX" > ICE_PROTO_XTR_ARG > "=3D[queue:]" > ICE_SAFE_MODE_SUPPORT_ARG "=3D<0|1>" > - ICE_PIPELINE_MODE_SUPPORT_ARG "=3D<0|1>"); > + ICE_PIPELINE_MODE_SUPPORT_ARG "=3D<0|1>" > + ICE_RX_LOW_LATENCY "=3D<0|1>"); >=20 > RTE_LOG_REGISTER_SUFFIX(ice_logtype_init, init, NOTICE); > RTE_LOG_REGISTER_SUFFIX(ice_logtype_driver, driver, NOTICE); diff --git > a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h index > ea9d892..26f5c56 100644 > --- a/drivers/net/ice/ice_ethdev.h > +++ b/drivers/net/ice/ice_ethdev.h > @@ -476,6 +476,7 @@ struct ice_pf { > * Cache devargs parse result. > */ > struct ice_devargs { > + int rx_low_latency; > int safe_mode_support; > uint8_t proto_xtr_dflt; > int pipe_mode_support; > -- > 1.8.3.1