From: "Zhang, Qi Z" <qi.z.zhang@intel.com>
To: "Liu, Lingyu" <lingyu.liu@intel.com>, "dev@dpdk.org" <dev@dpdk.org>
Cc: "Liu, Lingyu" <lingyu.liu@intel.com>
Subject: Re: [dpdk-dev] [PATCH v1] net/ixgbe: configure EXVET_T register
Date: Sat, 8 May 2021 01:57:12 +0000 [thread overview]
Message-ID: <3992a5f3439e4667b99cda1c31690fea@intel.com> (raw)
In-Reply-To: <20210429182343.52628-1-lingyu.liu@intel.com>
> -----Original Message-----
> From: dev <dev-bounces@dpdk.org> On Behalf Of Lingyu Liu
> Sent: Friday, April 30, 2021 2:24 AM
> To: dev@dpdk.org
> Cc: Liu, Lingyu <lingyu.liu@intel.com>
> Subject: [dpdk-dev] [PATCH v1] net/ixgbe: configure EXVET_T register
>
> According to X550 datasheet (section 8.2.1.2), when setting vlan tpid, the
> register EXVET_T on X550 NICs also need to be configured.
This looks like a fix, should we add fixline and cc stable?
>
> Signed-off-by: Lingyu Liu <lingyu.liu@intel.com>
> ---
> drivers/net/ixgbe/base/ixgbe_type.h | 1 +
> drivers/net/ixgbe/ixgbe_ethdev.c | 33 +++++++++++++++++++++++++++++
> 2 files changed, 34 insertions(+)
>
> diff --git a/drivers/net/ixgbe/base/ixgbe_type.h
> b/drivers/net/ixgbe/base/ixgbe_type.h
> index bc927a3..8e22be7 100644
> --- a/drivers/net/ixgbe/base/ixgbe_type.h
> +++ b/drivers/net/ixgbe/base/ixgbe_type.h
> @@ -151,6 +151,7 @@
> #define IXGBE_TCPTIMER 0x0004C
> #define IXGBE_CORESPARE 0x00600
> #define IXGBE_EXVET 0x05078
> +#define IXGBE_EXVET_T 0x08224
>
> /* NVM Registers */
> #define IXGBE_EEC 0x10010
> diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c
> b/drivers/net/ixgbe/ixgbe_ethdev.c
> index dcd7291..b9c89e8 100644
> --- a/drivers/net/ixgbe/ixgbe_ethdev.c
> +++ b/drivers/net/ixgbe/ixgbe_ethdev.c
> @@ -1925,6 +1925,39 @@ ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
> /* Only the high 16-bits is valid */
> IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
> IXGBE_EXVET_VET_EXT_SHIFT);
> + /* For X550, additional register need be set*/
> + switch (hw->device_id) {
> + case IXGBE_DEV_ID_X550T:
> + case IXGBE_DEV_ID_X550T1:
> + case IXGBE_DEV_ID_X550EM_A_KR:
> + case IXGBE_DEV_ID_X550EM_A_KR_L:
> + case IXGBE_DEV_ID_X550EM_A_SFP_N:
> + case IXGBE_DEV_ID_X550EM_A_SGMII:
> + case IXGBE_DEV_ID_X550EM_A_SGMII_L:
> + case IXGBE_DEV_ID_X550EM_A_10G_T:
> + case IXGBE_DEV_ID_X550EM_A_QSFP:
> + case IXGBE_DEV_ID_X550EM_A_QSFP_N:
> + case IXGBE_DEV_ID_X550EM_A_SFP:
> + case IXGBE_DEV_ID_X550EM_A_1G_T:
> + case IXGBE_DEV_ID_X550EM_A_1G_T_L:
> + case IXGBE_DEV_ID_X550EM_X_KX4:
> + case IXGBE_DEV_ID_X550EM_X_KR:
> + case IXGBE_DEV_ID_X550EM_X_SFP:
> + case IXGBE_DEV_ID_X550EM_X_10G_T:
> + case IXGBE_DEV_ID_X550EM_X_1G_T:
> + case IXGBE_DEV_ID_X550EM_X_XFI:
> + case IXGBE_DEV_ID_X550_VF_HV:
> + case IXGBE_DEV_ID_X550_VF:
> + case IXGBE_DEV_ID_X550EM_A_VF:
> + case IXGBE_DEV_ID_X550EM_A_VF_HV:
> + case IXGBE_DEV_ID_X550EM_X_VF:
> + case IXGBE_DEV_ID_X550EM_X_VF_HV:
> + IXGBE_WRITE_REG(hw, IXGBE_EXVET_T, (uint32_t)tpid <<
> + IXGBE_EXVET_VET_EXT_SHIFT);
> + break;
> + default:
> + break;
> + }
> } else {
> reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
> reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
> --
> 2.25.1
prev parent reply other threads:[~2021-05-08 1:57 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-29 18:23 Lingyu Liu
2021-05-08 1:57 ` Zhang, Qi Z [this message]
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