From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 84925A0A0E; Sat, 8 May 2021 03:57:18 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3F91640140; Sat, 8 May 2021 03:57:18 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mails.dpdk.org (Postfix) with ESMTP id 49DFD4013F for ; Sat, 8 May 2021 03:57:17 +0200 (CEST) IronPort-SDR: ePyCFapfYAi0paFCLo5kNME/JRUpv3wLIrpvK2DWjxTjW30TKeormZjM6uVv6yM1v2yGRvN3xS 9z+voF7CUWow== X-IronPort-AV: E=McAfee;i="6200,9189,9977"; a="178413398" X-IronPort-AV: E=Sophos;i="5.82,282,1613462400"; d="scan'208";a="178413398" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 May 2021 18:57:16 -0700 IronPort-SDR: LAUIzibkg9J+CjrJNNj02zY4k6Z+muA+XGISr0EutNpVaJzEmhGXD1RcobXDcuj/xK+AcwvEwk legENbG/JnpQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,282,1613462400"; d="scan'208";a="623075742" Received: from fmsmsx602.amr.corp.intel.com ([10.18.126.82]) by fmsmga005.fm.intel.com with ESMTP; 07 May 2021 18:57:15 -0700 Received: from shsmsx606.ccr.corp.intel.com (10.109.6.216) by fmsmsx602.amr.corp.intel.com (10.18.126.82) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Fri, 7 May 2021 18:57:14 -0700 Received: from shsmsx601.ccr.corp.intel.com (10.109.6.141) by SHSMSX606.ccr.corp.intel.com (10.109.6.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Sat, 8 May 2021 09:57:12 +0800 Received: from shsmsx601.ccr.corp.intel.com ([10.109.6.141]) by SHSMSX601.ccr.corp.intel.com ([10.109.6.141]) with mapi id 15.01.2106.013; Sat, 8 May 2021 09:57:12 +0800 From: "Zhang, Qi Z" To: "Liu, Lingyu" , "dev@dpdk.org" CC: "Liu, Lingyu" Thread-Topic: [dpdk-dev] [PATCH v1] net/ixgbe: configure EXVET_T register Thread-Index: AQHXPO25ffE0xxgofUi6iI6XqQ2N3KrY4POQ Date: Sat, 8 May 2021 01:57:12 +0000 Message-ID: <3992a5f3439e4667b99cda1c31690fea@intel.com> References: <20210429182343.52628-1-lingyu.liu@intel.com> In-Reply-To: <20210429182343.52628-1-lingyu.liu@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.5.1.3 dlp-product: dlpe-windows x-originating-ip: [10.239.127.36] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v1] net/ixgbe: configure EXVET_T register X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: dev On Behalf Of Lingyu Liu > Sent: Friday, April 30, 2021 2:24 AM > To: dev@dpdk.org > Cc: Liu, Lingyu > Subject: [dpdk-dev] [PATCH v1] net/ixgbe: configure EXVET_T register >=20 > According to X550 datasheet (section 8.2.1.2), when setting vlan tpid, th= e > register EXVET_T on X550 NICs also need to be configured. This looks like a fix, should we add fixline and cc stable? >=20 > Signed-off-by: Lingyu Liu > --- > drivers/net/ixgbe/base/ixgbe_type.h | 1 + > drivers/net/ixgbe/ixgbe_ethdev.c | 33 +++++++++++++++++++++++++++++ > 2 files changed, 34 insertions(+) >=20 > diff --git a/drivers/net/ixgbe/base/ixgbe_type.h > b/drivers/net/ixgbe/base/ixgbe_type.h > index bc927a3..8e22be7 100644 > --- a/drivers/net/ixgbe/base/ixgbe_type.h > +++ b/drivers/net/ixgbe/base/ixgbe_type.h > @@ -151,6 +151,7 @@ > #define IXGBE_TCPTIMER 0x0004C > #define IXGBE_CORESPARE 0x00600 > #define IXGBE_EXVET 0x05078 > +#define IXGBE_EXVET_T 0x08224 >=20 > /* NVM Registers */ > #define IXGBE_EEC 0x10010 > diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c > b/drivers/net/ixgbe/ixgbe_ethdev.c > index dcd7291..b9c89e8 100644 > --- a/drivers/net/ixgbe/ixgbe_ethdev.c > +++ b/drivers/net/ixgbe/ixgbe_ethdev.c > @@ -1925,6 +1925,39 @@ ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, > /* Only the high 16-bits is valid */ > IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid << > IXGBE_EXVET_VET_EXT_SHIFT); > + /* For X550, additional register need be set*/ > + switch (hw->device_id) { > + case IXGBE_DEV_ID_X550T: > + case IXGBE_DEV_ID_X550T1: > + case IXGBE_DEV_ID_X550EM_A_KR: > + case IXGBE_DEV_ID_X550EM_A_KR_L: > + case IXGBE_DEV_ID_X550EM_A_SFP_N: > + case IXGBE_DEV_ID_X550EM_A_SGMII: > + case IXGBE_DEV_ID_X550EM_A_SGMII_L: > + case IXGBE_DEV_ID_X550EM_A_10G_T: > + case IXGBE_DEV_ID_X550EM_A_QSFP: > + case IXGBE_DEV_ID_X550EM_A_QSFP_N: > + case IXGBE_DEV_ID_X550EM_A_SFP: > + case IXGBE_DEV_ID_X550EM_A_1G_T: > + case IXGBE_DEV_ID_X550EM_A_1G_T_L: > + case IXGBE_DEV_ID_X550EM_X_KX4: > + case IXGBE_DEV_ID_X550EM_X_KR: > + case IXGBE_DEV_ID_X550EM_X_SFP: > + case IXGBE_DEV_ID_X550EM_X_10G_T: > + case IXGBE_DEV_ID_X550EM_X_1G_T: > + case IXGBE_DEV_ID_X550EM_X_XFI: > + case IXGBE_DEV_ID_X550_VF_HV: > + case IXGBE_DEV_ID_X550_VF: > + case IXGBE_DEV_ID_X550EM_A_VF: > + case IXGBE_DEV_ID_X550EM_A_VF_HV: > + case IXGBE_DEV_ID_X550EM_X_VF: > + case IXGBE_DEV_ID_X550EM_X_VF_HV: > + IXGBE_WRITE_REG(hw, IXGBE_EXVET_T, (uint32_t)tpid << > + IXGBE_EXVET_VET_EXT_SHIFT); > + break; > + default: > + break; > + } > } else { > reg =3D IXGBE_READ_REG(hw, IXGBE_VLNCTRL); > reg =3D (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid; > -- > 2.25.1