From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id BF6EA2C4B for ; Thu, 28 Apr 2016 13:16:26 +0200 (CEST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP; 28 Apr 2016 04:16:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,546,1455004800"; d="scan'208";a="964555608" Received: from irsmsx152.ger.corp.intel.com ([163.33.192.66]) by orsmga002.jf.intel.com with ESMTP; 28 Apr 2016 04:16:26 -0700 Received: from irsmsx108.ger.corp.intel.com ([169.254.11.238]) by IRSMSX152.ger.corp.intel.com ([169.254.6.15]) with mapi id 14.03.0248.002; Thu, 28 Apr 2016 12:16:24 +0100 From: "Dumitrescu, Cristian" To: "Jastrzebski, MichalX K" , "Zhang, Roy Fan" , "Singh, Jasvinder" CC: "dev@dpdk.org" , "Mrozowicz, SlawomirX" Thread-Topic: [PATCH v3] examples/qos_sched: fix bad bit shift operation Thread-Index: AQHRm87xhFT3iqbbKkSWbjTGwcysi5+fRekQ Date: Thu, 28 Apr 2016 11:16:23 +0000 Message-ID: <3EB4FA525960D640B5BDFFD6A3D89126479A6F2B@IRSMSX108.ger.corp.intel.com> References: <1461244093-2008-1-git-send-email-michalx.k.jastrzebski@intel.com> <1461244093-2008-3-git-send-email-michalx.k.jastrzebski@intel.com> In-Reply-To: <1461244093-2008-3-git-send-email-michalx.k.jastrzebski@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiOTYxNDc5YjMtM2E4My00ZTAwLWFkOTYtMzE5NWIwOGRlYzgyIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6IkJibnk1OXp6VTErc21jWkJQY3VqSUZYejBEK3p5WFhONkthT1dzR3BqQlk9In0= x-ctpclassification: CTP_IC x-originating-ip: [163.33.239.180] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v3] examples/qos_sched: fix bad bit shift operation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Apr 2016 11:16:27 -0000 > -----Original Message----- > From: Jastrzebski, MichalX K > Sent: Thursday, April 21, 2016 2:08 PM > To: Dumitrescu, Cristian ; Zhang, Roy Fan > ; Singh, Jasvinder > Cc: dev@dpdk.org; Mrozowicz, SlawomirX > > Subject: [PATCH v3] examples/qos_sched: fix bad bit shift operation >=20 > From: Slawomir Mrozowicz >=20 > Fix issue reported by Coverity. >=20 > Coverity ID 30690: Bad bit shift operation > large_shift: In expression 1ULL << i, left shifting by more than 63 bits > has undefined behavior. The shift amount, i, is as much as 127. >=20 > Fixes: de3cfa2c9823 ("sched: initial import") >=20 > Signed-off-by: Slawomir Mrozowicz > --- > examples/qos_sched/args.c | 84 +++++++++++++++++++++++++++++------ > ------------ > 1 file changed, 52 insertions(+), 32 deletions(-) >=20 > diff --git a/examples/qos_sched/args.c b/examples/qos_sched/args.c > index 3e7fd08..cd077ba 100644 > --- a/examples/qos_sched/args.c > +++ b/examples/qos_sched/args.c > @@ -53,7 +53,7 @@ >=20 > static uint32_t app_master_core =3D 1; > static uint32_t app_numa_mask; > -static uint64_t app_used_core_mask =3D 0; > +static int app_used_core_mask[RTE_MAX_LCORE]; > static uint64_t app_used_port_mask =3D 0; > static uint64_t app_used_rx_port_mask =3D 0; > static uint64_t app_used_tx_port_mask =3D 0; > @@ -115,22 +115,23 @@ static inline int str_is(const char *str, const cha= r *is) > return strcmp(str, is) =3D=3D 0; > } >=20 > -/* returns core mask used by DPDK */ > -static uint64_t > -app_eal_core_mask(void) > +/* compare used core with eal configuration, > + returns: > + 1 if equal > + 0 if differ */ > +static int > +app_eal_core_check(void) > { > - uint32_t i; > - uint64_t cm =3D 0; > + uint16_t i; > + int ret =3D 1; > struct rte_config *cfg =3D rte_eal_get_configuration(); >=20 > - for (i =3D 0; i < RTE_MAX_LCORE; i++) { > - if (cfg->lcore_role[i] =3D=3D ROLE_RTE) > - cm |=3D (1ULL << i); > + for (i =3D 0; i < RTE_MAX_LCORE && ret; i++) { > + if ((cfg->lcore_role[i] =3D=3D ROLE_RTE) !=3D > app_used_core_mask[i]) > + ret =3D 0; > } >=20 > - cm |=3D (1ULL << cfg->master_lcore); > - > - return cm; > + return ret; > } >=20 >=20 > @@ -292,14 +293,9 @@ app_parse_flow_conf(const char *conf_str) > app_used_tx_port_mask |=3D mask; > app_used_port_mask |=3D mask; >=20 > - mask =3D 1lu << pconf->rx_core; > - app_used_core_mask |=3D mask; > - > - mask =3D 1lu << pconf->wt_core; > - app_used_core_mask |=3D mask; > - > - mask =3D 1lu << pconf->tx_core; > - app_used_core_mask |=3D mask; > + app_used_core_mask[pconf->rx_core] =3D 1; > + app_used_core_mask[pconf->wt_core] =3D 1; > + app_used_core_mask[pconf->tx_core] =3D 1; >=20 > nb_pfc++; >=20 > @@ -335,7 +331,7 @@ app_parse_args(int argc, char **argv) > int option_index; > const char *optname; > char *prgname =3D argv[0]; > - uint32_t i, nb_lcores; > + uint16_t i, j, k, nb_lcores; >=20 > static struct option lgopts[] =3D { > { "pfc", 1, 0, 0 }, > @@ -349,6 +345,9 @@ app_parse_args(int argc, char **argv) > { NULL, 0, 0, 0 } > }; >=20 > + for (i =3D 0; i < RTE_MAX_LCORE; i++) > + app_used_core_mask[i] =3D 0; > + > /* initialize EAL first */ > ret =3D rte_eal_init(argc, argv); > if (ret < 0) > @@ -436,19 +435,40 @@ app_parse_args(int argc, char **argv) > } >=20 > /* check master core index validity */ > - for(i =3D 0; i <=3D app_master_core; i++) { > - if (app_used_core_mask & (1u << app_master_core)) { > - RTE_LOG(ERR, APP, "Master core index is not > configured properly\n"); > - app_usage(prgname); > - return -1; > - } > + if (app_used_core_mask[app_master_core] =3D=3D 1) { > + RTE_LOG(ERR, APP, > + "Master core index is not configured properly\n"); > + app_usage(prgname); > + return -1; > } > - app_used_core_mask |=3D 1u << app_master_core; > + app_used_core_mask[app_master_core] =3D 1; > + > + if ((app_eal_core_check() =3D=3D 0) || > + (app_master_core !=3D rte_get_master_lcore())) { > + > + char used_hexstr[RTE_MAX_LCORE/4+1]; > + char conf_hexstr[RTE_MAX_LCORE/4+1]; > + int used_byte, conf_byte; > + struct rte_config *cfg =3D rte_eal_get_configuration(); > + > + for (i =3D 0; i < RTE_MAX_LCORE/4; i++) { > + used_byte =3D 0; > + conf_byte =3D 0; > + for (j =3D 0; j < 3; j++) { > + k =3D 4 * (RTE_MAX_LCORE/4 - i - 1) + j; > + used_byte +=3D app_used_core_mask[k] << j; > + conf_byte +=3D > + ((cfg->lcore_role[k] =3D=3D > + ROLE_RTE)?1:0) << j; > + } > + sprintf(&used_hexstr[i], "%1x", used_byte); > + sprintf(&conf_hexstr[i], "%1x", used_byte); > + } > + > + RTE_LOG(ERR, APP, "EAL core mask not configured > properly\n"); > + RTE_LOG(ERR, APP, " must be : %s\n", used_hexstr); > + RTE_LOG(ERR, APP, " instead of: %s\n", conf_hexstr); >=20 > - if ((app_used_core_mask !=3D app_eal_core_mask()) || > - (app_master_core !=3D rte_get_master_lcore())) { > - RTE_LOG(ERR, APP, "EAL core mask not configured properly, > must be %" PRIx64 > - " instead of %" PRIx64 "\n" , > app_used_core_mask, app_eal_core_mask()); > return -1; > } >=20 > -- > 1.9.1 Can you please explain the root issue? This patch contains way too much code for fixing a shift overflow issue, it= is basically a rework without explaining the issue or reason/benefit for t= he rework. This approach does not look right to me, I am sure there is a better and qu= icker way to fix the potential issue once we all understand it.