* [dpdk-dev] [PATCH] net/softnic: fix ipv6 address from big endian to cpu order
@ 2018-09-28 16:18 Reshma Pattan
2018-09-28 16:18 ` [dpdk-dev] [PATCH] examples/ip_pipeline: fix ipv6 address endianness Reshma Pattan
2018-10-08 15:27 ` [dpdk-dev] [PATCH] net/softnic: fix ipv6 address from big endian to cpu order Dumitrescu, Cristian
0 siblings, 2 replies; 4+ messages in thread
From: Reshma Pattan @ 2018-09-28 16:18 UTC (permalink / raw)
To: dev, cristian.dumitrescu, jasvinder.singh; +Cc: Reshma Pattan
Fix ipv6 endianness from big endian to cpu order.
Fixes: ee19326a4b ("net/softnic: add command for pipeline table entries")
Signed-off-by: Reshma Pattan <reshma.pattan@intel.com>
---
drivers/net/softnic/rte_eth_softnic_thread.c | 40 ++++++++++++--------
1 file changed, 24 insertions(+), 16 deletions(-)
diff --git a/drivers/net/softnic/rte_eth_softnic_thread.c b/drivers/net/softnic/rte_eth_softnic_thread.c
index 8a1509030..2be81900a 100644
--- a/drivers/net/softnic/rte_eth_softnic_thread.c
+++ b/drivers/net/softnic/rte_eth_softnic_thread.c
@@ -2202,29 +2202,37 @@ match_convert(struct softnic_table_rule_match *mh,
ml->acl_add.field_value[0].mask_range.u8 =
mh->match.acl.proto_mask;
- ml->acl_add.field_value[1].value.u32 = sa32[0];
+ ml->acl_add.field_value[1].value.u32 =
+ rte_be_to_cpu_32(sa32[0]);
ml->acl_add.field_value[1].mask_range.u32 =
sa32_depth[0];
- ml->acl_add.field_value[2].value.u32 = sa32[1];
+ ml->acl_add.field_value[2].value.u32 =
+ rte_be_to_cpu_32(sa32[1]);
ml->acl_add.field_value[2].mask_range.u32 =
sa32_depth[1];
- ml->acl_add.field_value[3].value.u32 = sa32[2];
+ ml->acl_add.field_value[3].value.u32 =
+ rte_be_to_cpu_32(sa32[2]);
ml->acl_add.field_value[3].mask_range.u32 =
sa32_depth[2];
- ml->acl_add.field_value[4].value.u32 = sa32[3];
+ ml->acl_add.field_value[4].value.u32 =
+ rte_be_to_cpu_32(sa32[3]);
ml->acl_add.field_value[4].mask_range.u32 =
sa32_depth[3];
- ml->acl_add.field_value[5].value.u32 = da32[0];
+ ml->acl_add.field_value[5].value.u32 =
+ rte_be_to_cpu_32(da32[0]);
ml->acl_add.field_value[5].mask_range.u32 =
da32_depth[0];
- ml->acl_add.field_value[6].value.u32 = da32[1];
+ ml->acl_add.field_value[6].value.u32 =
+ rte_be_to_cpu_32(da32[1]);
ml->acl_add.field_value[6].mask_range.u32 =
da32_depth[1];
- ml->acl_add.field_value[7].value.u32 = da32[2];
+ ml->acl_add.field_value[7].value.u32 =
+ rte_be_to_cpu_32(da32[2]);
ml->acl_add.field_value[7].mask_range.u32 =
da32_depth[2];
- ml->acl_add.field_value[8].value.u32 = da32[3];
+ ml->acl_add.field_value[8].value.u32 =
+ rte_be_to_cpu_32(da32[3]);
ml->acl_add.field_value[8].mask_range.u32 =
da32_depth[3];
@@ -2264,36 +2272,36 @@ match_convert(struct softnic_table_rule_match *mh,
mh->match.acl.proto_mask;
ml->acl_delete.field_value[1].value.u32 =
- sa32[0];
+ rte_be_to_cpu_32(sa32[0]);
ml->acl_delete.field_value[1].mask_range.u32 =
sa32_depth[0];
ml->acl_delete.field_value[2].value.u32 =
- sa32[1];
+ rte_be_to_cpu_32(sa32[1]);
ml->acl_delete.field_value[2].mask_range.u32 =
sa32_depth[1];
ml->acl_delete.field_value[3].value.u32 =
- sa32[2];
+ rte_be_to_cpu_32(sa32[2]);
ml->acl_delete.field_value[3].mask_range.u32 =
sa32_depth[2];
ml->acl_delete.field_value[4].value.u32 =
- sa32[3];
+ rte_be_to_cpu_32(sa32[3]);
ml->acl_delete.field_value[4].mask_range.u32 =
sa32_depth[3];
ml->acl_delete.field_value[5].value.u32 =
- da32[0];
+ rte_be_to_cpu_32(da32[0]);
ml->acl_delete.field_value[5].mask_range.u32 =
da32_depth[0];
ml->acl_delete.field_value[6].value.u32 =
- da32[1];
+ rte_be_to_cpu_32(da32[1]);
ml->acl_delete.field_value[6].mask_range.u32 =
da32_depth[1];
ml->acl_delete.field_value[7].value.u32 =
- da32[2];
+ rte_be_to_cpu_32(da32[2]);
ml->acl_delete.field_value[7].mask_range.u32 =
da32_depth[2];
ml->acl_delete.field_value[8].value.u32 =
- da32[3];
+ rte_be_to_cpu_32(da32[3]);
ml->acl_delete.field_value[8].mask_range.u32 =
da32_depth[3];
--
2.17.1
^ permalink raw reply [flat|nested] 4+ messages in thread* [dpdk-dev] [PATCH] examples/ip_pipeline: fix ipv6 address endianness
2018-09-28 16:18 [dpdk-dev] [PATCH] net/softnic: fix ipv6 address from big endian to cpu order Reshma Pattan
@ 2018-09-28 16:18 ` Reshma Pattan
2018-10-08 15:28 ` Dumitrescu, Cristian
2018-10-08 15:27 ` [dpdk-dev] [PATCH] net/softnic: fix ipv6 address from big endian to cpu order Dumitrescu, Cristian
1 sibling, 1 reply; 4+ messages in thread
From: Reshma Pattan @ 2018-09-28 16:18 UTC (permalink / raw)
To: dev, cristian.dumitrescu, jasvinder.singh; +Cc: Reshma Pattan
Fix ipv6 endianness from big endian to cpu order.
Fixes: a3a95b7d58 ("examples/ip_pipeline: add table entry commands")
Signed-off-by: Reshma Pattan <reshma.pattan@intel.com>
---
examples/ip_pipeline/thread.c | 40 +++++++++++++++++++++--------------
1 file changed, 24 insertions(+), 16 deletions(-)
diff --git a/examples/ip_pipeline/thread.c b/examples/ip_pipeline/thread.c
index 7fc03332e..b00ea0653 100644
--- a/examples/ip_pipeline/thread.c
+++ b/examples/ip_pipeline/thread.c
@@ -2244,29 +2244,37 @@ match_convert(struct table_rule_match *mh,
ml->acl_add.field_value[0].mask_range.u8 =
mh->match.acl.proto_mask;
- ml->acl_add.field_value[1].value.u32 = sa32[0];
+ ml->acl_add.field_value[1].value.u32 =
+ rte_be_to_cpu_32(sa32[0]);
ml->acl_add.field_value[1].mask_range.u32 =
sa32_depth[0];
- ml->acl_add.field_value[2].value.u32 = sa32[1];
+ ml->acl_add.field_value[2].value.u32 =
+ rte_be_to_cpu_32(sa32[1]);
ml->acl_add.field_value[2].mask_range.u32 =
sa32_depth[1];
- ml->acl_add.field_value[3].value.u32 = sa32[2];
+ ml->acl_add.field_value[3].value.u32 =
+ rte_be_to_cpu_32(sa32[2]);
ml->acl_add.field_value[3].mask_range.u32 =
sa32_depth[2];
- ml->acl_add.field_value[4].value.u32 = sa32[3];
+ ml->acl_add.field_value[4].value.u32 =
+ rte_be_to_cpu_32(sa32[3]);
ml->acl_add.field_value[4].mask_range.u32 =
sa32_depth[3];
- ml->acl_add.field_value[5].value.u32 = da32[0];
+ ml->acl_add.field_value[5].value.u32 =
+ rte_be_to_cpu_32(da32[0]);
ml->acl_add.field_value[5].mask_range.u32 =
da32_depth[0];
- ml->acl_add.field_value[6].value.u32 = da32[1];
+ ml->acl_add.field_value[6].value.u32 =
+ rte_be_to_cpu_32(da32[1]);
ml->acl_add.field_value[6].mask_range.u32 =
da32_depth[1];
- ml->acl_add.field_value[7].value.u32 = da32[2];
+ ml->acl_add.field_value[7].value.u32 =
+ rte_be_to_cpu_32(da32[2]);
ml->acl_add.field_value[7].mask_range.u32 =
da32_depth[2];
- ml->acl_add.field_value[8].value.u32 = da32[3];
+ ml->acl_add.field_value[8].value.u32 =
+ rte_be_to_cpu_32(da32[3]);
ml->acl_add.field_value[8].mask_range.u32 =
da32_depth[3];
@@ -2308,36 +2316,36 @@ match_convert(struct table_rule_match *mh,
mh->match.acl.proto_mask;
ml->acl_delete.field_value[1].value.u32 =
- sa32[0];
+ rte_be_to_cpu_32(sa32[0]);
ml->acl_delete.field_value[1].mask_range.u32 =
sa32_depth[0];
ml->acl_delete.field_value[2].value.u32 =
- sa32[1];
+ rte_be_to_cpu_32(sa32[1]);
ml->acl_delete.field_value[2].mask_range.u32 =
sa32_depth[1];
ml->acl_delete.field_value[3].value.u32 =
- sa32[2];
+ rte_be_to_cpu_32(sa32[2]);
ml->acl_delete.field_value[3].mask_range.u32 =
sa32_depth[2];
ml->acl_delete.field_value[4].value.u32 =
- sa32[3];
+ rte_be_to_cpu_32(sa32[3]);
ml->acl_delete.field_value[4].mask_range.u32 =
sa32_depth[3];
ml->acl_delete.field_value[5].value.u32 =
- da32[0];
+ rte_be_to_cpu_32(da32[0]);
ml->acl_delete.field_value[5].mask_range.u32 =
da32_depth[0];
ml->acl_delete.field_value[6].value.u32 =
- da32[1];
+ rte_be_to_cpu_32(da32[1]);
ml->acl_delete.field_value[6].mask_range.u32 =
da32_depth[1];
ml->acl_delete.field_value[7].value.u32 =
- da32[2];
+ rte_be_to_cpu_32(da32[2]);
ml->acl_delete.field_value[7].mask_range.u32 =
da32_depth[2];
ml->acl_delete.field_value[8].value.u32 =
- da32[3];
+ rte_be_to_cpu_32(da32[3]);
ml->acl_delete.field_value[8].mask_range.u32 =
da32_depth[3];
--
2.17.1
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [dpdk-dev] [PATCH] examples/ip_pipeline: fix ipv6 address endianness
2018-09-28 16:18 ` [dpdk-dev] [PATCH] examples/ip_pipeline: fix ipv6 address endianness Reshma Pattan
@ 2018-10-08 15:28 ` Dumitrescu, Cristian
0 siblings, 0 replies; 4+ messages in thread
From: Dumitrescu, Cristian @ 2018-10-08 15:28 UTC (permalink / raw)
To: Pattan, Reshma, dev, Singh, Jasvinder
> -----Original Message-----
> From: Pattan, Reshma
> Sent: Friday, September 28, 2018 5:19 PM
> To: dev@dpdk.org; Dumitrescu, Cristian <cristian.dumitrescu@intel.com>;
> Singh, Jasvinder <jasvinder.singh@intel.com>
> Cc: Pattan, Reshma <reshma.pattan@intel.com>
> Subject: [PATCH] examples/ip_pipeline: fix ipv6 address endianness
>
> Fix ipv6 endianness from big endian to cpu order.
>
> Fixes: a3a95b7d58 ("examples/ip_pipeline: add table entry commands")
>
> Signed-off-by: Reshma Pattan <reshma.pattan@intel.com>
> ---
> examples/ip_pipeline/thread.c | 40 +++++++++++++++++++++--------------
> 1 file changed, 24 insertions(+), 16 deletions(-)
>
Acked-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
Applied on next-pipeline tree, thanks!
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [dpdk-dev] [PATCH] net/softnic: fix ipv6 address from big endian to cpu order
2018-09-28 16:18 [dpdk-dev] [PATCH] net/softnic: fix ipv6 address from big endian to cpu order Reshma Pattan
2018-09-28 16:18 ` [dpdk-dev] [PATCH] examples/ip_pipeline: fix ipv6 address endianness Reshma Pattan
@ 2018-10-08 15:27 ` Dumitrescu, Cristian
1 sibling, 0 replies; 4+ messages in thread
From: Dumitrescu, Cristian @ 2018-10-08 15:27 UTC (permalink / raw)
To: Pattan, Reshma, dev, Singh, Jasvinder
> -----Original Message-----
> From: Pattan, Reshma
> Sent: Friday, September 28, 2018 5:19 PM
> To: dev@dpdk.org; Dumitrescu, Cristian <cristian.dumitrescu@intel.com>;
> Singh, Jasvinder <jasvinder.singh@intel.com>
> Cc: Pattan, Reshma <reshma.pattan@intel.com>
> Subject: [PATCH] net/softnic: fix ipv6 address from big endian to cpu order
>
> Fix ipv6 endianness from big endian to cpu order.
>
> Fixes: ee19326a4b ("net/softnic: add command for pipeline table entries")
>
> Signed-off-by: Reshma Pattan <reshma.pattan@intel.com>
> ---
> drivers/net/softnic/rte_eth_softnic_thread.c | 40 ++++++++++++--------
> 1 file changed, 24 insertions(+), 16 deletions(-)
>
Applied on next-pipeline tree, thanks!
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2018-10-08 15:29 UTC | newest]
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2018-09-28 16:18 [dpdk-dev] [PATCH] net/softnic: fix ipv6 address from big endian to cpu order Reshma Pattan
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