From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by dpdk.org (Postfix) with ESMTP id 2A8681BE05 for ; Thu, 20 Dec 2018 20:10:43 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Dec 2018 11:10:42 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,378,1539673200"; d="scan'208";a="102231256" Received: from irsmsx154.ger.corp.intel.com ([163.33.192.96]) by orsmga006.jf.intel.com with ESMTP; 20 Dec 2018 11:10:41 -0800 Received: from irsmsx108.ger.corp.intel.com ([169.254.11.26]) by IRSMSX154.ger.corp.intel.com ([169.254.12.217]) with mapi id 14.03.0415.000; Thu, 20 Dec 2018 19:10:40 +0000 From: "Dumitrescu, Cristian" To: Tonghao Zhang , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH 1/2] sched: refine get base helper function Thread-Index: AQHUhyIracbxLodckE2dRIp0xPNYyaWIIM2g Date: Thu, 20 Dec 2018 19:10:39 +0000 Message-ID: <3EB4FA525960D640B5BDFFD6A3D891268E818016@IRSMSX108.ger.corp.intel.com> References: <1543413355-2874-1-git-send-email-xiangxia.m.yue@gmail.com> In-Reply-To: <1543413355-2874-1-git-send-email-xiangxia.m.yue@gmail.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiOWQ3Mjg3ZTctYjE4YS00YTI0LWI3ZDktYTQ3MTY1Y2I2YTEwIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiNGt5MUNzNkE0V252dGdMSjRxMHBGTXQwQWJ1T0Jwa2phSXFYRTR1SVhMZzFhc2JhYkk2Q1FBZ2t4ZE5BM1dQNiJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [163.33.239.181] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH 1/2] sched: refine get base helper function X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 20 Dec 2018 19:10:43 -0000 > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Tonghao Zhang > Sent: Wednesday, November 28, 2018 1:56 PM > To: dev@dpdk.org > Cc: Tonghao Zhang > Subject: [dpdk-dev] [PATCH 1/2] sched: refine get base helper function >=20 > use switch instead of if, and it is more easy reading. >=20 > Signed-off-by: Tonghao Zhang > --- > lib/librte_sched/rte_sched.c | 40 +++++++++++++++++++-------------------= -- > 1 file changed, 19 insertions(+), 21 deletions(-) >=20 > diff --git a/lib/librte_sched/rte_sched.c b/lib/librte_sched/rte_sched.c > index 587d5e6..17de6e6 100644 > --- a/lib/librte_sched/rte_sched.c > +++ b/lib/librte_sched/rte_sched.c > @@ -385,7 +385,7 @@ enum rte_sched_port_array { > uint32_t n_subports_per_port =3D params->n_subports_per_port; > uint32_t n_pipes_per_subport =3D params->n_pipes_per_subport; > uint32_t n_pipes_per_port =3D n_pipes_per_subport * > n_subports_per_port; > - uint32_t n_queues_per_port =3D RTE_SCHED_QUEUES_PER_PIPE * > n_pipes_per_subport * n_subports_per_port; > + uint32_t n_queues_per_port =3D RTE_SCHED_QUEUES_PER_PIPE * > n_pipes_per_port; >=20 > uint32_t size_subport =3D n_subports_per_port * sizeof(struct > rte_sched_subport); > uint32_t size_pipe =3D n_pipes_per_port * sizeof(struct > rte_sched_pipe); > @@ -407,35 +407,33 @@ enum rte_sched_port_array { > size_queue_array =3D n_pipes_per_port * > size_per_pipe_queue_array; >=20 > base =3D 0; > + switch (array) { > + case e_RTE_SCHED_PORT_ARRAY_TOTAL: > + base +=3D RTE_CACHE_LINE_ROUNDUP(size_queue_array); >=20 > - if (array =3D=3D e_RTE_SCHED_PORT_ARRAY_SUBPORT) > - return base; > - base +=3D RTE_CACHE_LINE_ROUNDUP(size_subport); > + case e_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY: > + base +=3D RTE_CACHE_LINE_ROUNDUP(size_bmp_array); >=20 > - if (array =3D=3D e_RTE_SCHED_PORT_ARRAY_PIPE) > - return base; > - base +=3D RTE_CACHE_LINE_ROUNDUP(size_pipe); > + case e_RTE_SCHED_PORT_ARRAY_BMP_ARRAY: > + base +=3D RTE_CACHE_LINE_ROUNDUP(size_pipe_profiles); >=20 > - if (array =3D=3D e_RTE_SCHED_PORT_ARRAY_QUEUE) > - return base; > - base +=3D RTE_CACHE_LINE_ROUNDUP(size_queue); > + case e_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES: > + base +=3D RTE_CACHE_LINE_ROUNDUP(size_queue_extra); >=20 > - if (array =3D=3D e_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA) > - return base; > - base +=3D RTE_CACHE_LINE_ROUNDUP(size_queue_extra); > + case e_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA: > + base +=3D RTE_CACHE_LINE_ROUNDUP(size_queue); >=20 > - if (array =3D=3D e_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES) > - return base; > - base +=3D RTE_CACHE_LINE_ROUNDUP(size_pipe_profiles); > + case e_RTE_SCHED_PORT_ARRAY_QUEUE: > + base +=3D RTE_CACHE_LINE_ROUNDUP(size_pipe); >=20 > - if (array =3D=3D e_RTE_SCHED_PORT_ARRAY_BMP_ARRAY) > - return base; > - base +=3D RTE_CACHE_LINE_ROUNDUP(size_bmp_array); > + case e_RTE_SCHED_PORT_ARRAY_PIPE: > + base +=3D RTE_CACHE_LINE_ROUNDUP(size_subport); >=20 > - if (array =3D=3D e_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY) > + case e_RTE_SCHED_PORT_ARRAY_SUBPORT: > return base; > - base +=3D RTE_CACHE_LINE_ROUNDUP(size_queue_array); > + } >=20 > + RTE_LOG(DEBUG, SCHED, "Should not reach here. \n"); > return base; > } >=20 > -- > 1.8.3.1 NAK. Sorry, but I completely disagree: to me, using the pattern you describe mak= es the code much harder to read as opposed to simpler to read.