From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 903BDA04FF; Thu, 24 Mar 2022 10:09:22 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 68D71410FC; Thu, 24 Mar 2022 10:09:22 +0100 (CET) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mails.dpdk.org (Postfix) with ESMTP id 239CB40141 for ; Thu, 24 Mar 2022 10:09:20 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1648112961; x=1679648961; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=C2TGnk99nzUslyXDxdtFY+Vpgg5JrgG3nzvLPfIyG8k=; b=I7qgKZromRxCS3Pc1IeFcH/o4EczEg9O5juQhFG+8sLqGPPUnfjYNPX4 JaVzCR0vzqWraK6/vyTj/OKh1FGosIGgNQBhaHn1YSyYSHIJWCFTTYfhB 5idBL8DHxsw4HFgEdS6bbcMqNalcgI4y2mNPik0wcOt3DUFUYbFst8I4C RcmLNk7VucKTXKaW9sQQYtQPNZbUI4DyjcxMTuGFr0ZHMBdiczMnIpcbA Jgw/kfCz3YDSJEDFoe5z7wT+FKpfddfAx0PyaC7niFh9clr8emISZWuN7 KGG/E4JWlnRqPxcZp9ATNn93BXSpdgm8QBdYRxcym7U0m2S8OijHFxNPx A==; X-IronPort-AV: E=McAfee;i="6200,9189,10295"; a="238267377" X-IronPort-AV: E=Sophos;i="5.90,206,1643702400"; d="scan'208";a="238267377" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2022 02:09:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,206,1643702400"; d="scan'208";a="519704315" Received: from fmsmsx602.amr.corp.intel.com ([10.18.126.82]) by orsmga006.jf.intel.com with ESMTP; 24 Mar 2022 02:09:17 -0700 Received: from shsmsx602.ccr.corp.intel.com (10.109.6.142) by fmsmsx602.amr.corp.intel.com (10.18.126.82) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.27; Thu, 24 Mar 2022 02:09:15 -0700 Received: from shsmsx601.ccr.corp.intel.com (10.109.6.141) by SHSMSX602.ccr.corp.intel.com (10.109.6.142) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.21; Thu, 24 Mar 2022 17:09:13 +0800 Received: from shsmsx601.ccr.corp.intel.com ([10.109.6.141]) by SHSMSX601.ccr.corp.intel.com ([10.109.6.141]) with mapi id 15.01.2308.021; Thu, 24 Mar 2022 17:09:13 +0800 From: "Zhang, Qi Z" To: "Wu, Wenjun1" , "dev@dpdk.org" , "Yang, Qiming" CC: "Van Haaren, Harry" , "Su, Simei" Subject: RE: [PATCH v4] net/ice: improve performance of RX timestamp offload Thread-Topic: [PATCH v4] net/ice: improve performance of RX timestamp offload Thread-Index: AQHYLHjBI/Bf0CjKsECAt2ezZnbUUazOZCXQ Date: Thu, 24 Mar 2022 09:09:13 +0000 Message-ID: <3da8efff430e43808657c353c748ea9d@intel.com> References: <20220222062612.335622-1-wenjun1.wu@intel.com> <20220228073607.2249410-1-wenjun1.wu@intel.com> In-Reply-To: <20220228073607.2249410-1-wenjun1.wu@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.6.401.20 dlp-product: dlpe-windows x-originating-ip: [10.239.127.36] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > -----Original Message----- > From: Wu, Wenjun1 > Sent: Monday, February 28, 2022 3:36 PM > To: dev@dpdk.org; Zhang, Qi Z ; Yang, Qiming > > Cc: Van Haaren, Harry ; Su, Simei > ; Wu, Wenjun1 > Subject: [PATCH v4] net/ice: improve performance of RX timestamp offload >=20 > Previously, each time a burst of packets is received, SW reads HW registe= r > and assembles it and the timestamp from descriptor together to get the > complete 64 bits timestamp. >=20 > This patch optimizes the algorithm. The SW only needs to check the > monotonicity of the low 32bits timestamp to avoid crossing borders. > Each time before SW receives a burst of packets, it should check the time > difference between current time and last update time to avoid the low 32 > bits timestamp cycling twice. >=20 > Signed-off-by: Wenjun Wu Added cc stable Acked-by: Qi Zhang Applied to dpdk-next-net-intel. Thanks Qi