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DIR:OUT; SFP:1101; SCL:1; SRVR:CY4PR1101MB2311; H:CY4PR1101MB2183.namprd11.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: V0fzKzRQSl4mkB4bDD6b5a5a+/Sd1FUUm5zIT7ZaNtXWCPC6TftYBpcOBuUiXwvtAgGtXuT8xKJbEIQf2YG2MeTuj72a/2Nb/WTCHPn3t8wCpijhTTSmiXsmuLMWSjYdinq5fGWSDsFhPOTsugy1ORCY4uB8+ye0oWiqrorQCJ5GGcizEbQtryOY35x1MhuOyulgtyNatvtPu+3sZCW25SCeK2U+G3TmzF63gnzrpsv4iMjhi8Wa98p9CGa6oQk4n8QYpG51tgKeLdUtgUYZ+1k9oR0XHhIDpBIAe8w4PmDQ1WsMKG6XwY3xiME1SAr16YWPB9N3IGDC+oDNUCPrGeJLp/JVqVllhNor4Ohf3vDHCHrW3HVm+8cDBJruxYYPt7d+EGBZkZe3FO6VZye230z7Q0TupO6zLq82ea1ZgL6mm4ss/SmEDTsAMtziEFhT Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2f646984-014f-459c-03fc-08d759744fc4 X-MS-Exchange-CrossTenant-originalarrivaltime: 25 Oct 2019 17:53:58.7818 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Aw7hudOrjLBWZJtBZdMPYWJ50LD80J2jsLOKsQeoWtG/RVFjp4hQ7EH9TDncmuKRmCGXs5QPGncY9lIvURx60g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR1101MB2311 Subject: [dpdk-dev] [RFC v2 3/7] net/atlantic: Add helper functions for PHY access X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavel Belous Aquantia AQC107/AQC108 ethernet controllers includes MAC and PHY part. Some network features, like MACSec, are configured directly in the PHY part= . This patch adds helper functions for accessing PHY part via internal MDIO i= nterface. Signed-off-by: Pavel Belous --- drivers/net/atlantic/Makefile | 2 + drivers/net/atlantic/macsec/mdio.c | 328 +++++++++++++++++++++++++++++++++= ++++ drivers/net/atlantic/macsec/mdio.h | 19 +++ drivers/net/atlantic/meson.build | 1 + 4 files changed, 350 insertions(+) create mode 100644 drivers/net/atlantic/macsec/mdio.c create mode 100644 drivers/net/atlantic/macsec/mdio.h diff --git a/drivers/net/atlantic/Makefile b/drivers/net/atlantic/Makefile index fc12e6a..6340588 100644 --- a/drivers/net/atlantic/Makefile +++ b/drivers/net/atlantic/Makefile @@ -21,6 +21,7 @@ LDLIBS +=3D -lrte_ethdev -lrte_net LDLIBS +=3D -lrte_bus_pci =20 VPATH +=3D $(SRCDIR)/hw_atl +VPATH +=3D $(SRCDIR)/macsec =20 # # all source are stored in SRCS-y @@ -33,5 +34,6 @@ SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) +=3D hw_atl_llh.c SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) +=3D hw_atl_utils_fw2x.c SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) +=3D hw_atl_b0.c SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) +=3D rte_pmd_atlantic.c +SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) +=3D mdio.c =20 include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/net/atlantic/macsec/mdio.c b/drivers/net/atlantic/macs= ec/mdio.c new file mode 100644 index 0000000..a662f58 --- /dev/null +++ b/drivers/net/atlantic/macsec/mdio.c @@ -0,0 +1,328 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Aquantia Corporation + */ + +#include "errno.h" +#include "../atl_hw_regs.h" +#include "../atl_logs.h" +#include "../hw_atl/hw_atl_llh.h" +#include "../hw_atl/hw_atl_b0.h" +#include "../hw_atl/hw_atl_b0_internal.h" +#include "mdio.h" + +static inline uint32_t macValRead(uint32_t reg, uint32_t msk, uint32_t shi= ft) +{ + return (reg & msk) >> shift; +} + +static inline void macValWrite(uint32_t* reg, uint32_t msk, uint32_t shift= , uint32_t val) +{ + *reg =3D (*reg & ~msk) | (val << shift); +} + +static inline uint32_t macBitRead(uint32_t reg, uint32_t msk) +{ + return reg & msk; +} + +static inline uint32_t regGlobalMdioInterface1Get(void *hw) +{ + return aq_hw_read_reg(hw, 0x280); +} + +static inline void valGlobalMdioInterface1MdioClockEnableSet(uint32_t *reg= , uint32_t val) +{ + macValWrite(reg, 0x00004000, 14, val); +} + +static inline void regGlobalMdioInterface1Set(void *hw, uint32_t val) +{ + aq_hw_write_reg(hw, 0x280, val); +} + +static inline void valGlobalMdioInterface4MdioAddressSet(uint32_t *reg, ui= nt32_t val) +{ + macValWrite(reg, 0x0000FFFF, 0, val); +} + +static inline void regGlobalMdioInterface4Set(void *hw, uint32_t val) +{ + aq_hw_write_reg(hw, 0x28C, val); +} + +static inline void valGlobalMdioInterface2MdioExecuteOperationSet(uint32_t= *reg, uint32_t val) +{ + macValWrite(reg, 0x00008000, 15, val); +} + +static inline void valGlobalMdioInterface2MdioOpModeSet(uint32_t *reg, uin= t32_t val) +{ + macValWrite(reg, 0x00003000, 12, val); +} + +static inline void valGlobalMdioInterface2MdioPhyAddressSet(uint32_t *reg,= uint32_t val) +{ + macValWrite(reg, 0x000003FF, 0, val); +} + +static inline void regGlobalMdioInterface2Set(void *hw, uint32_t val) +{ + aq_hw_write_reg(hw, 0x284, val); +} + +static inline uint32_t regGlobalMdioInterface2Get(void *hw) +{ + return aq_hw_read_reg(hw, 0x284); +} + +static inline void valGlobalMdioInterface3MdioWriteDataSet(uint32_t *reg, = uint32_t val) +{ + macValWrite(reg, 0x0000FFFF, 0, val); +} + +static inline void regGlobalMdioInterface3Set(void *hw, uint32_t val) +{ + aq_hw_write_reg(hw, 0x288, val); +} + +static inline uint32_t regGlobalMdioInterface5Get(void *hw) +{ + return aq_hw_read_reg(hw, 0x290); +} + +static inline uint32_t valGlobalMdioInterface5MdioReadDataGet(uint32_t reg= ) +{ + return macValRead(reg, 0x0000FFFF, 0); +} + +static inline uint32_t bitGlobalMdioInterface2MdioBusyGet(uint32_t reg) +{ + return macBitRead(reg, 0x80000000); +} + + +/* Operation Mode for MDIO */ +#define MDIO_OP_NO 0 /* No Op */ +#define MDIO_OP_READ 1 /* Read Op */ +#define MDIO_OP_WRITE 2 /* Write Op */ +#define MDIO_OP_ADDR 3 /* Address Op */ + +#define MDIO_COMMAND_TIMEOUT 100 +#define MDIO_SEMAPHORE_TIMEOUT_MS 30 /* msec. */ + + +/* 32 bits command + 32 bits preamble =3D 64 */ +#define MDIO_ONE_CMD_CLOCK_TICKS 64 +/* Wait 10 MDIO transactions */ +#define TIMEOUT_BUSY_WAIT_COUNT ((MIPS_COUNT_HZ * MDIO_ONE_CMD_CLOCK_T= ICKS / MDIO_HZ) * 10) + +static int mdio_phy_addr =3D (0 << 5); + + +static inline unsigned int mMdioBusyCheck(void *hw) +{ + return bitGlobalMdioInterface2MdioBusyGet(regGlobalMdioInterface2Get(h= w)); +} + +static int mBusyWait(struct aq_hw_s *hw) +{ + unsigned i =3D 0; + + for (i =3D 1000U; mMdioBusyCheck(hw) && i; i--){}; + + if (i =3D=3D 0) { + PMD_DRV_LOG(ERR, "Mdio busy!!"); + return 1; + } + + return 0; +} + + +static inline void mSendPhyAddress(struct aq_hw_s *hw, unsigned int mmd, u= nsigned int addr) +{ + uint32_t reg; + + /* Set MDIO Address (0x28c) */ + reg =3D 0; + valGlobalMdioInterface4MdioAddressSet(®, addr); + regGlobalMdioInterface4Set(hw, reg); + + /* Set MDIO Address Operation and PHY Address (0x284) */ + reg =3D 0; + valGlobalMdioInterface2MdioExecuteOperationSet(®, 1); + valGlobalMdioInterface2MdioOpModeSet(®, MDIO_OP_ADDR); + valGlobalMdioInterface2MdioPhyAddressSet(®, mdio_phy_addr | mmd); + regGlobalMdioInterface2Set(hw, reg); +} + +static void mSendDummyWriteCmd(struct aq_hw_s *hw) +{ + uint32_t reg; + + // Set data (0x288) + reg =3D 0; + valGlobalMdioInterface3MdioWriteDataSet(®, 0); + regGlobalMdioInterface3Set(hw, reg); + + // Write operation (0x284) + reg =3D 0; + valGlobalMdioInterface2MdioExecuteOperationSet(®, 1); + valGlobalMdioInterface2MdioOpModeSet(®, MDIO_OP_WRITE); + valGlobalMdioInterface2MdioPhyAddressSet(®, 0); + regGlobalMdioInterface2Set(hw, reg); +} + +static inline void mSendReadCmd(struct aq_hw_s *hw, unsigned int mmd) +{ + uint32_t reg; + + // Execute Read Operation (0x284) + reg =3D 0; + valGlobalMdioInterface2MdioExecuteOperationSet(®, 1); + valGlobalMdioInterface2MdioOpModeSet(®, MDIO_OP_READ); + valGlobalMdioInterface2MdioPhyAddressSet(®, mdio_phy_addr | mmd); + regGlobalMdioInterface2Set(hw, reg); +} + +static inline void mSendWriteCmd(struct aq_hw_s *hw, unsigned int mmd) +{ + uint32_t reg; + + // Execute Read Operation (0x284) + reg =3D 0; + valGlobalMdioInterface2MdioExecuteOperationSet(®, 1); + valGlobalMdioInterface2MdioOpModeSet(®, MDIO_OP_WRITE); + valGlobalMdioInterface2MdioPhyAddressSet(®, mdio_phy_addr | mmd); + regGlobalMdioInterface2Set(hw, reg); +} + +static inline unsigned short int mReadData(struct aq_hw_s *hw) +{ + // Register 0x290 + return valGlobalMdioInterface5MdioReadDataGet(regGlobalMdioInterface5G= et(hw)); +} + +static inline void mWriteData(struct aq_hw_s *hw, unsigned short int val) +{ + uint32_t reg; + + // Register 0x288 + reg =3D 0; + valGlobalMdioInterface3MdioWriteDataSet(®, val); + regGlobalMdioInterface3Set(hw, reg); +} + + +static int __mdioRead(struct aq_hw_s *hw, unsigned int mmd, unsigned int a= ddr, unsigned short int* data) +{ + int ret =3D -1; + + /* Execute Address Operation */ + if (mBusyWait(hw)) + goto _exit; + mSendPhyAddress(hw, mmd, addr); + + /* Dummy write transaction */ + if (mBusyWait(hw)) + goto _exit; + mSendDummyWriteCmd(hw); + + /* Read command */ + if (mBusyWait(hw)) + goto _exit; + mSendReadCmd(hw, mmd); + + /* Read MDIO Data */ + if (mBusyWait(hw)) + goto _exit; + *data =3D mReadData(hw); + + ret =3D 0; + +_exit: + return ret; +} + +static +int __mdioWrite(struct aq_hw_s *hw, unsigned int mmd, unsigned int addr, u= nsigned short int data) +{ + int ret =3D -1; + + /* Execute Address Operation */ + if (mBusyWait(hw)) + goto _exit; + mSendPhyAddress(hw, mmd, addr); + + /* Dummy write transaction */ + if (mBusyWait(hw)) + goto _exit; + mSendDummyWriteCmd(hw); + + /* Write command */ + if (mBusyWait(hw)) + goto _exit; + mWriteData(hw, data); + mSendWriteCmd(hw, mmd); + + /* Expect completion of the operation */ + if (mBusyWait(hw)) + goto _exit; + + ret =3D 0; + +_exit: + return ret; +} + +int mdioRead(struct aq_hw_s *hw, unsigned int mmd, unsigned int addr, unsi= gned short int* data) +{ + uint32_t reg; + int ret; + + // Send Dummy Transaction + if (mBusyWait(hw)) + return -1; + mSendDummyWriteCmd(hw); + + // Enable MDIO Clock (active low) (0x280) + reg =3D regGlobalMdioInterface1Get(hw); + valGlobalMdioInterface1MdioClockEnableSet(®, 0); + regGlobalMdioInterface1Set(hw, reg); + + ret =3D __mdioRead(hw, mmd, addr, data); + + // Disable MDIO Clock (0x280) + reg =3D regGlobalMdioInterface1Get(hw); + valGlobalMdioInterface1MdioClockEnableSet(®, 1); + regGlobalMdioInterface1Set(hw, reg); + + return ret; +} + +int mdioWrite(struct aq_hw_s *hw, unsigned int mmd, unsigned int addr, uns= igned short int data) +{ + uint32_t reg; + int ret; + + // Send Dummy Transaction + if (mBusyWait(hw)) + return -1; + mSendDummyWriteCmd(hw); + + // Enable MDIO Clock (active low) (0x280) + reg =3D regGlobalMdioInterface1Get(hw); + valGlobalMdioInterface1MdioClockEnableSet(®, 0); + regGlobalMdioInterface1Set(hw, reg); + + ret =3D __mdioWrite(hw, mmd, addr, data); + + // Disable MDIO Clock (0x280) + reg =3D regGlobalMdioInterface1Get(hw); + valGlobalMdioInterface1MdioClockEnableSet(®, 1); + regGlobalMdioInterface1Set(hw, reg); + + return ret; +} + + diff --git a/drivers/net/atlantic/macsec/mdio.h b/drivers/net/atlantic/macs= ec/mdio.h new file mode 100644 index 0000000..907f04f --- /dev/null +++ b/drivers/net/atlantic/macsec/mdio.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Aquantia Corporation + */ + +#ifndef __MDIO_HH__ +#define __MDIO_HH__ + + +#include "../atl_types.h" +#include "../hw_atl/hw_atl_utils.h" + + +#define MMD_GLOBAL 0x1E + + +int mdioRead(struct aq_hw_s *hw, unsigned int mmd, unsigned int addr, unsi= gned short int* data); +int mdioWrite(struct aq_hw_s *hw, unsigned int mmd, unsigned int addr, uns= igned short int data); + +#endif diff --git a/drivers/net/atlantic/meson.build b/drivers/net/atlantic/meson.= build index 919d741..d1c66f4 100644 --- a/drivers/net/atlantic/meson.build +++ b/drivers/net/atlantic/meson.build @@ -12,4 +12,5 @@ sources =3D files( 'hw_atl/hw_atl_utils_fw2x.c', 'hw_atl/hw_atl_utils.c', 'rte_pmd_atlantic.c', + 'macsec/mdio.c', ) --=20 2.7.4