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Tue, 27 Feb 2024 11:56:59 -0500 X-MC-Unique: JoqLOiEcOBGBLVpYF6Wz7Q-1 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 8FECC3814E93; Tue, 27 Feb 2024 16:56:58 +0000 (UTC) Received: from [10.39.208.20] (unknown [10.39.208.20]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 0AE461121312; Tue, 27 Feb 2024 16:56:56 +0000 (UTC) Message-ID: <3f692a3a-b0a2-40cd-b367-317f9f582e2f@redhat.com> Date: Tue, 27 Feb 2024 17:56:55 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] baseband/fpga_5gnr_fec: use new barrier API From: Maxime Coquelin To: "roretzla@linux.microsoft.com" References: <20240222162113.1896370-1-maxime.coquelin@redhat.com> <99571564-348b-45b6-b07e-32ffbb89faee@redhat.com> Cc: "Chautru, Nicolas" , "dev@dpdk.org" , "Vargas, Hernan" , "thomas@monjalon.net" , "Marchand, David" Autocrypt: addr=maxime.coquelin@redhat.com; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Hi Tyler, On 2/26/24 12:03, Maxime Coquelin wrote: > Hello, > > On 2/22/24 19:05, Chautru, Nicolas wrote: >> Hi Maxime, >> >> Why would we change this here and now? Is the intent not to use new >> suggested semantics for new patches only? > > The pull request was rejected because of the use of such barrier, which > is reported by checkpatch. > > ### [PATCH] baseband/fpga_5gnr_fec: add AGX100 support > Warning in drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c: > Using rte_smp_[r/w]mb > >> Are all DPDK drivers being changed? > > My understanding is that for now, only new occurrences are prohibited, > can you confirm Tyler? Could you please clarify whether conversion for existing rte_smp_rmb() calls to rte_atomic_thread_fence() in drivers is planned, or only new occurrences are prohibited? Thanks in advances, Maxime > If so we could only change for now the patch adding ACX100. > But... I preferred doing the changes for all bbdev drivers for > consistency. > >> I am unsure we would want to change these drivers, this is kind of >> risk introduced by code churn that gets ecosystem unwilling to move to >> latest version. > > I think it is better to change now that we are far from the next LTS. > >> These memory barriers issues are awful to troubleshoot or properly >> validate, so personally quite reluctant to change. > > If I disassemble fpga_dequeue_enc() with and without the patch, I cannot > spot a difference. > > Thomas, are you waiting for this series to be applied to take the pull > request that was initially for -rc1? > > Thanks, > Maxime > >> Thanks >> Nic >> >>> -----Original Message----- >>> From: Maxime Coquelin >>> Sent: Thursday, February 22, 2024 8:21 AM >>> To: dev@dpdk.org; Chautru, Nicolas ; Vargas, >>> Hernan ; Marchand, David >>> ; thomas@monjalon.net; >>> roretzla@linux.microsoft.com >>> Cc: Maxime Coquelin >>> Subject: [PATCH 1/2] baseband/fpga_5gnr_fec: use new barrier API >>> >>> rte_smp_rmb() is deprecated, use the new API instead as suggested in >>> rte_atomic header. >>> >>> Signed-off-by: Maxime Coquelin >>> --- >>>   drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c | 8 ++++---- >>>   1 file changed, 4 insertions(+), 4 deletions(-) >>> >>> diff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c >>> b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c >>> index efc1d3a772..314c87350e 100644 >>> --- a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c >>> +++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c >>> @@ -2661,7 +2661,7 @@ vc_5gnr_dequeue_ldpc_enc_one_op_cb(struct >>> fpga_5gnr_queue *q, struct rte_bbdev_e >>>           return -1; >>> >>>       /* make sure the response is read atomically */ >>> -    rte_smp_rmb(); >>> +    rte_atomic_thread_fence(rte_memory_order_acquire); >>> >>>       rte_bbdev_log_debug("DMA response desc %p", desc); >>> >>> @@ -2690,7 +2690,7 @@ agx100_dequeue_ldpc_enc_one_op_cb(struct >>> fpga_5gnr_queue *q, struct rte_bbdev_en >>>           return -1; >>> >>>       /* make sure the response is read atomically. */ >>> -    rte_smp_rmb(); >>> +    rte_atomic_thread_fence(rte_memory_order_acquire); >>> >>>       rte_bbdev_log_debug("DMA response desc %p", desc); >>> >>> @@ -2722,7 +2722,7 @@ vc_5gnr_dequeue_ldpc_dec_one_op_cb(struct >>> fpga_5gnr_queue *q, struct rte_bbdev_d >>>           return -1; >>> >>>       /* make sure the response is read atomically */ >>> -    rte_smp_rmb(); >>> +    rte_atomic_thread_fence(rte_memory_order_acquire); >>> >>>   #ifdef RTE_LIBRTE_BBDEV_DEBUG >>>       vc_5gnr_print_dma_dec_desc_debug_info(desc); >>> @@ -2768,7 +2768,7 @@ agx100_dequeue_ldpc_dec_one_op_cb(struct >>> fpga_5gnr_queue *q, struct rte_bbdev_de >>>           return -1; >>> >>>       /* make sure the response is read atomically. */ >>> -    rte_smp_rmb(); >>> +    rte_atomic_thread_fence(rte_memory_order_acquire); >>> >>>   #ifdef RTE_LIBRTE_BBDEV_DEBUG >>>       agx100_print_dma_dec_desc_debug_info(desc); >>> -- >>> 2.43.0 >>