From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com [148.163.129.52]) by dpdk.org (Postfix) with ESMTP id 5D3BB25E5 for ; Wed, 29 Nov 2017 10:49:51 +0100 (CET) Received: from pure.maildistiller.com (dispatch1.mdlocal [10.7.20.164]) by dispatch1-us1.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with ESMTP id EDD1360ED0; Wed, 29 Nov 2017 09:49:49 +0000 (UTC) X-Virus-Scanned: Proofpoint Essentials engine Received: from mx1-us3.ppe-hosted.com (us4-filterqueue.mdlocal [10.7.20.246]) by pure.maildistiller.com (Proofpoint Essentials ESMTP Server) with ESMTPS id 613F428004D; Wed, 29 Nov 2017 09:49:49 +0000 (UTC) Received: from webmail.solarflare.com (uk.solarflare.com [193.34.186.16]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1-us3.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with ESMTPS id 1C3EDB40056; Wed, 29 Nov 2017 09:49:49 +0000 (UTC) Received: from [192.168.239.128] (193.34.186.16) by ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Wed, 29 Nov 2017 09:49:40 +0000 To: Ferruh Yigit , CC: Andrew Jackson References: <1510819481-6809-1-git-send-email-arybchenko@solarflare.com> <1510819481-6809-2-git-send-email-arybchenko@solarflare.com> <69a7d813-9443-0a1b-5fef-432260439aa3@intel.com> From: Andrew Rybchenko Message-ID: <3f6b9321-30d4-1161-68f3-82c517a929db@solarflare.com> Date: Wed, 29 Nov 2017 12:49:37 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.4.0 MIME-Version: 1.0 In-Reply-To: <69a7d813-9443-0a1b-5fef-432260439aa3@intel.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US X-Originating-IP: [193.34.186.16] X-ClientProxiedBy: ocex03.SolarFlarecom.com (10.20.40.36) To ukex01.SolarFlarecom.com (10.17.10.4) X-TM-AS-Product-Ver: SMEX-11.0.0.1191-8.100.1062-23498.003 X-TM-AS-Result: No--15.748600-0.000000-31 X-TM-AS-User-Approved-Sender: Yes X-TM-AS-User-Blocked-Sender: No X-MDID: 1511948989-zJu-XcUTc3-e Subject: Re: [dpdk-dev] [PATCH 01/53] net/sfc/base: copy new header from firmwaresrc X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 29 Nov 2017 09:49:51 -0000 On 11/27/2017 10:58 PM, Ferruh Yigit wrote: > On 11/16/2017 12:03 AM, Andrew Rybchenko wrote: >> From: Andrew Jackson >> >> Signed-off-by: Andrew Jackson >> Signed-off-by: Andrew Rybchenko >> --- >> drivers/net/sfc/base/siena_flash.h | 12 +++++++++--- >> 1 file changed, 9 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/net/sfc/base/siena_flash.h b/drivers/net/sfc/base/siena_flash.h >> index e2700554..5fa3ea4 100644 >> --- a/drivers/net/sfc/base/siena_flash.h >> +++ b/drivers/net/sfc/base/siena_flash.h >> @@ -113,15 +113,21 @@ typedef struct siena_mc_boot_hdr_s { /* GENERATED BY scripts/genfwdef */ >> efx_word_t checksum; /* of whole header area + firmware image */ >> efx_word_t firmware_version_d; >> efx_byte_t mcfw_subtype; >> - efx_byte_t generation; /* Valid for medford, SBZ for earlier chips */ >> + efx_byte_t generation; /* MC (Medford and later): MC partition generation when */ >> + /* written to NVRAM. */ >> + /* MUM & SUC images: subtype. */ >> + /* (Otherwise set to 0) */ >> efx_dword_t firmware_text_offset; /* offset to firmware .text */ >> efx_dword_t firmware_text_size; /* length of firmware .text, in bytes */ >> efx_dword_t firmware_data_offset; /* offset to firmware .data */ >> efx_dword_t firmware_data_size; /* length of firmware .data, in bytes */ >> efx_byte_t spi_rate; /* SPI rate for reading image, 0 is BootROM default */ >> efx_byte_t spi_phase_adj; /* SPI SDO/SCL phase adjustment, 0 is default (no adj) */ >> - efx_word_t xpm_sector; /* The sector that contains the key, or 0xffff if unsigned (medford) SBZ (earlier) */ >> - efx_dword_t reserved_c[7]; /* (set to 0) */ >> + efx_word_t xpm_sector; /* XPM (MEDFORD and later): The sector that contains */ >> + /* the key, or 0xffff if unsigned. (Otherwise set to 0) */ >> + efx_byte_t mumfw_subtype; /* MUM & SUC images: subtype. (Otherwise set to 0) */ > Does this means there is a new updated FW? Should user know about version of it, > or is FW upgrade needs to be documented somewhere? No, it just defines some fields in reserved space. So, it does not change size. In fact the new field is not used directly and useful for other tools based on libefx. Hopefully it will not generate too much traffic on the mailing list. >> + efx_byte_t reserved_b[3]; /* (set to 0) */ >> + efx_dword_t reserved_c[6]; /* (set to 0) */ >> } siena_mc_boot_hdr_t; >> >> #define SIENA_MC_BOOT_HDR_PADDING \ >> >>