From: Maxime Coquelin <maxime.coquelin@redhat.com>
To: Xueming Li <xuemingl@nvidia.com>, Matan Azrad <matan@nvidia.com>,
Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Cc: dev@dpdk.org, Asaf Penso <asafp@nvidia.com>,
matan@mellanox.com, stable@dpdk.org
Subject: Re: [dpdk-dev] [PATCH v1 2/2] vdpa/mlx5: specify lag port affinity
Date: Thu, 29 Oct 2020 09:29:52 +0100 [thread overview]
Message-ID: <4000bcb8-c338-352b-556f-bca6dddb240d@redhat.com> (raw)
In-Reply-To: <1603881879-19275-2-git-send-email-xuemingl@nvidia.com>
On 10/28/20 11:44 AM, Xueming Li wrote:
> If set TIS lag port affinity to auto, firmware assign port affinity on
> each creation with Round Robin. In case of 2 PFs, if create virtq,
> destroy and create again, then each virtq will get same port affinity.
>
> To resolve this fw limitation, this patch sets create TIS with specified
> affinity for each PF.
>
> Fixes: bff735011078 ("vdpa/mlx5: prepare virtio queues")
> Cc: matan@mellanox.com
> Cc: stable@dpdk.org
>
> Signed-off-by: Xueming Li <xuemingl@nvidia.com>
> Acked-by: Matan Azrad <matan@nvidia.com>
> Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
> ---
> drivers/vdpa/mlx5/mlx5_vdpa.c | 3 +++
> drivers/vdpa/mlx5/mlx5_vdpa.h | 3 ++-
> drivers/vdpa/mlx5/mlx5_vdpa_virtq.c | 23 ++++++++++++++---------
> 3 files changed, 19 insertions(+), 10 deletions(-)
Applied to dpdk-next-virtio/main.
Thanks!
Maxime
prev parent reply other threads:[~2020-10-29 8:30 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-26 11:10 [dpdk-dev] [PATCH 1/2] common/mlx5: get number of ports that can be bonded Xueming Li
2020-10-26 11:10 ` [dpdk-dev] [PATCH 2/2] vdpa/mlx5: specify lag port affinity Xueming Li
2020-10-28 9:35 ` Maxime Coquelin
2020-10-28 10:32 ` Xueming(Steven) Li
2020-10-28 9:30 ` [dpdk-dev] [PATCH 1/2] common/mlx5: get number of ports that can be bonded Maxime Coquelin
2020-10-28 10:44 ` [dpdk-dev] [PATCH v1 " Xueming Li
2020-10-29 8:29 ` Maxime Coquelin
2020-10-28 10:44 ` [dpdk-dev] [PATCH v1 2/2] vdpa/mlx5: specify lag port affinity Xueming Li
2020-10-29 8:29 ` Maxime Coquelin [this message]
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