From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id DF06CA04F1; Mon, 6 Jan 2020 16:11:36 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C6B8E1D6A9; Mon, 6 Jan 2020 16:11:28 +0100 (CET) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id 9E4D81D581 for ; Mon, 6 Jan 2020 05:01:46 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Jan 2020 20:01:45 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,401,1571727600"; d="scan'208";a="302768769" Received: from orsmsx109.amr.corp.intel.com ([10.22.240.7]) by orsmga001.jf.intel.com with ESMTP; 05 Jan 2020 20:01:45 -0800 Received: from orsmsx111.amr.corp.intel.com ([169.254.12.24]) by ORSMSX109.amr.corp.intel.com ([169.254.11.176]) with mapi id 14.03.0439.000; Sun, 5 Jan 2020 20:01:45 -0800 From: "Patil, Kiran" To: "Zhang, Qi Z" , "Yang, Qiming" CC: "dev@dpdk.org" , "Ye, Xiaolong" , "Stillwell Jr, Paul M" Thread-Topic: [PATCH v2 09/12] net/ice/base: change fdir desc preparation Thread-Index: AQHVxEJ4394jb6AXZ0evMbD1b+HwgafdA3fA Date: Mon, 6 Jan 2020 04:01:44 +0000 Message-ID: <4197C471DCF8714FBA1FE32565271C1401486B1809@ORSMSX111.amr.corp.intel.com> References: <20191205123847.39579-1-qi.z.zhang@intel.com> <20200106033851.43978-1-qi.z.zhang@intel.com> <20200106033851.43978-10-qi.z.zhang@intel.com> In-Reply-To: <20200106033851.43978-10-qi.z.zhang@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZmY1YWQ2ZTYtZWJlOC00OTQyLTg5YzQtNGExMTY4YWZjZTJkIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoieEJiZ2dmUmZwUkFzdE5sZDNZZlV5M2ZJdlQrZlVHZ3R6UmYxNk5vc1ZqNkNWbEJXYnlHekZcLzBEUk90YVp3dWsifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.22.254.139] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-Mailman-Approved-At: Mon, 06 Jan 2020 16:11:25 +0100 Subject: Re: [dpdk-dev] [PATCH v2 09/12] net/ice/base: change fdir desc preparation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" ACK -----Original Message----- From: Zhang, Qi Z =20 Sent: Sunday, January 5, 2020 7:39 PM To: Yang, Qiming Cc: dev@dpdk.org; Ye, Xiaolong ; Zhang, Qi Z ; Patil, Kiran ; Stillwell Jr, Paul M= Subject: [PATCH v2 09/12] net/ice/base: change fdir desc preparation Change internal implemenatation of how FD filter programming desc is prepar= ed. This is to minimize the amount of code needed to prep the FD filter pro= gramming desc (avoid memcpy, etc...) and just use predefined shifts and mas= k. This type of change are needed to expedite FD setup during data path (AD= Q uses this codepath during initial flow setup) and it will also be useful = when adding side-band flow-director filter. Signed-off-by: Kiran Patil Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang Acked-by: Qiming Yang --- drivers/net/ice/base/ice_fdir.c | 92 ++++++++++++++++++++++++-------------= ---- 1 file changed, 55 insertions(+), 37 deletions(-) diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdi= r.c index 37b388169..87fa0afba 100644 --- a/drivers/net/ice/base/ice_fdir.c +++ b/drivers/net/ice/base/ice_fdir.c @@ -352,35 +352,6 @@ static const struct ice_fdir_base_pkt ice_fdir_pkt[] = =3D { =20 #define ICE_FDIR_NUM_PKT ARRAY_SIZE(ice_fdir_pkt) =20 -/* Flow Direcotr (FD) filter program descriptor Context */ -static const s= truct ice_ctx_ele ice_fd_fltr_desc_ctx_info[] =3D { - /* Field Width LSB */ - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, qindex, 11, 0), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, comp_q, 1, 11), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, comp_report, 2, 12), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, fd_space, 2, 14), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, cnt_index, 13, 16), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, cnt_ena, 2, 29), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, evict_ena, 1, 31), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, toq, 3, 32), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, toq_prio, 3, 35), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, dpu_recipe, 2, 38), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, drop, 1, 40), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, flex_prio, 3, 41), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, flex_mdid, 4, 44), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, flex_val, 16, 48), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, dtype, 4, 64), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, pcmd, 1, 68), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, desc_prof_prio, 3, 69), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, desc_prof, 6, 72), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, fd_vsi, 10, 78), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, swap, 1, 88), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, fdid_prio, 3, 89), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, fdid_mdid, 4, 92), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, fdid, 32, 96), - { 0 } -}; - /** * ice_set_dflt_val_fd_desc * @fd_fltr_ctx: pointer to fd filter descriptor @@ -455,19 +426,66 @@ ice= _fdir_get_prgm_desc(struct ice_hw *hw, struct ice_fdir_fltr *input, =20 /** * ice_set_fd_desc_val - * @fd_fltr_ctx: pointer to fd filter descriptor context + * @ctx: pointer to fd filter descriptor context * @fdir_desc: populated with fd filter descriptor values */ void -ice_set_fd_desc_val(struct ice_fd_fltr_desc_ctx *fd_fltr_ctx, +ice_set_fd_desc_val(struct ice_fd_fltr_desc_ctx *ctx, struct ice_fltr_desc *fdir_desc) { - u64 ctx_buf[2] =3D { 0 }; - - ice_set_ctx((u8 *)fd_fltr_ctx, (u8 *)ctx_buf, - ice_fd_fltr_desc_ctx_info); - fdir_desc->qidx_compq_space_stat =3D CPU_TO_LE64(ctx_buf[0]); - fdir_desc->dtype_cmd_vsi_fdid =3D CPU_TO_LE64(ctx_buf[1]); + u64 qword; + + /* prep QW0 of FD filter programming desc */ + qword =3D ((u64)ctx->qindex << ICE_FXD_FLTR_QW0_QINDEX_S) & + ICE_FXD_FLTR_QW0_QINDEX_M; + qword |=3D ((u64)ctx->comp_q << ICE_FXD_FLTR_QW0_COMP_Q_S) & + ICE_FXD_FLTR_QW0_COMP_Q_M; + qword |=3D ((u64)ctx->comp_report << ICE_FXD_FLTR_QW0_COMP_REPORT_S) & + ICE_FXD_FLTR_QW0_COMP_REPORT_M; + qword |=3D ((u64)ctx->fd_space << ICE_FXD_FLTR_QW0_FD_SPACE_S) & + ICE_FXD_FLTR_QW0_FD_SPACE_M; + qword |=3D ((u64)ctx->cnt_index << ICE_FXD_FLTR_QW0_STAT_CNT_S) & + ICE_FXD_FLTR_QW0_STAT_CNT_M; + qword |=3D ((u64)ctx->cnt_ena << ICE_FXD_FLTR_QW0_STAT_ENA_S) & + ICE_FXD_FLTR_QW0_STAT_ENA_M; + qword |=3D ((u64)ctx->evict_ena << ICE_FXD_FLTR_QW0_EVICT_ENA_S) & + ICE_FXD_FLTR_QW0_EVICT_ENA_M; + qword |=3D ((u64)ctx->toq << ICE_FXD_FLTR_QW0_TO_Q_S) & + ICE_FXD_FLTR_QW0_TO_Q_M; + qword |=3D ((u64)ctx->toq_prio << ICE_FXD_FLTR_QW0_TO_Q_PRI_S) & + ICE_FXD_FLTR_QW0_TO_Q_PRI_M; + qword |=3D ((u64)ctx->dpu_recipe << ICE_FXD_FLTR_QW0_DPU_RECIPE_S) & + ICE_FXD_FLTR_QW0_DPU_RECIPE_M; + qword |=3D ((u64)ctx->drop << ICE_FXD_FLTR_QW0_DROP_S) & + ICE_FXD_FLTR_QW0_DROP_M; + qword |=3D ((u64)ctx->flex_prio << ICE_FXD_FLTR_QW0_FLEX_PRI_S) & + ICE_FXD_FLTR_QW0_FLEX_PRI_M; + qword |=3D ((u64)ctx->flex_mdid << ICE_FXD_FLTR_QW0_FLEX_MDID_S) & + ICE_FXD_FLTR_QW0_FLEX_MDID_M; + qword |=3D ((u64)ctx->flex_val << ICE_FXD_FLTR_QW0_FLEX_VAL_S) & + ICE_FXD_FLTR_QW0_FLEX_VAL_M; + fdir_desc->qidx_compq_space_stat =3D CPU_TO_LE64(qword); + + /* prep QW1 of FD filter programming desc */ + qword =3D ((u64)ctx->dtype << ICE_FXD_FLTR_QW1_DTYPE_S) & + ICE_FXD_FLTR_QW1_DTYPE_M; + qword |=3D ((u64)ctx->pcmd << ICE_FXD_FLTR_QW1_PCMD_S) & + ICE_FXD_FLTR_QW1_PCMD_M; + qword |=3D ((u64)ctx->desc_prof_prio << ICE_FXD_FLTR_QW1_PROF_PRI_S) & + ICE_FXD_FLTR_QW1_PROF_PRI_M; + qword |=3D ((u64)ctx->desc_prof << ICE_FXD_FLTR_QW1_PROF_S) & + ICE_FXD_FLTR_QW1_PROF_M; + qword |=3D ((u64)ctx->fd_vsi << ICE_FXD_FLTR_QW1_FD_VSI_S) & + ICE_FXD_FLTR_QW1_FD_VSI_M; + qword |=3D ((u64)ctx->swap << ICE_FXD_FLTR_QW1_SWAP_S) & + ICE_FXD_FLTR_QW1_SWAP_M; + qword |=3D ((u64)ctx->fdid_prio << ICE_FXD_FLTR_QW1_FDID_PRI_S) & + ICE_FXD_FLTR_QW1_FDID_PRI_M; + qword |=3D ((u64)ctx->fdid_mdid << ICE_FXD_FLTR_QW1_FDID_MDID_S) & + ICE_FXD_FLTR_QW1_FDID_MDID_M; + qword |=3D ((u64)ctx->fdid << ICE_FXD_FLTR_QW1_FDID_S) & + ICE_FXD_FLTR_QW1_FDID_M; + fdir_desc->dtype_cmd_vsi_fdid =3D CPU_TO_LE64(qword); } =20 /** -- 2.13.6