From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 79190454EF; Tue, 25 Jun 2024 13:18:09 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3240C42D27; Tue, 25 Jun 2024 13:15:58 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) by mails.dpdk.org (Postfix) with ESMTP id 2CCD9427D4 for ; Tue, 25 Jun 2024 13:15:36 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719314136; x=1750850136; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zA6ZBiMoWYhw3nRgj8aqGUFga/G/beVyb1Zn6UGn/ns=; b=S7hnNAtuYtx1hAOtT0/pejz5M4D+8uRzR8/0Mif/UbnCBCCy6t/i0cQg 4k2iQhTHGvE38UcNLMAYnP1FGdp/XQCH40zVmviHnM30yifB6PnCrZjwI m8kwm/7G5y9OBORLRmV9xdOi6AAgWiNTxYy4rEdnLCHuzbFInkBpP37kH /gjdJfe/LTX8XdNy4tZ4xfHou3+xf08Ji8wNze4+jmiRo9IW2+R1WOzrq qt75Y01SplL+Vz8rzyAZ85A336ykv0yY2oFbTG+U417LvGBOkiWt5ysAJ IDaKPuignwVe4Fyv3PPyQUyqzAjSmTjoqsRQd2IZckOUxl8F3rv2yv9SN w==; X-CSE-ConnectionGUID: 5fd6qQUlTreWpv163kgdzQ== X-CSE-MsgGUID: JaHyvB+uQM+P/rPBDo5wBA== X-IronPort-AV: E=McAfee;i="6700,10204,11113"; a="16080110" X-IronPort-AV: E=Sophos;i="6.08,263,1712646000"; d="scan'208";a="16080110" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2024 04:15:35 -0700 X-CSE-ConnectionGUID: qof0IRECRbChkqnrJFlk+A== X-CSE-MsgGUID: TNtM812+SE26h7pzTsP1aA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,263,1712646000"; d="scan'208";a="43719027" Received: from unknown (HELO silpixa00401119.ir.intel.com) ([10.55.129.167]) by orviesa009.jf.intel.com with ESMTP; 25 Jun 2024 04:15:35 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Sergey Temerkhanov , bruce.richardson@intel.com, ian.stokes@intel.com, Grzegorz Nitka Subject: [PATCH v3 022/129] net/ice/base: use model-dependent number of PHY ports Date: Tue, 25 Jun 2024 12:12:27 +0100 Message-ID: <4230b15b9c1566bf6d528a7b6824a4a342c79e58.1719313663.git.anatoly.burakov@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sergey Temerkhanov Set up and use model-dependent number of PHY ports. Also fix iterations over PTP ports. Define 'max_phy_port', a new ice_hw struct member to store the max port number handled by given clock owner. Replace 'phy_ports' with 'max_phy_port' for max range in iterations over PTP ports in case of ETH56G based devices. Signed-off-by: Sergey Temerkhanov Signed-off-by: Grzegorz Nitka Signed-off-by: Ian Stokes --- drivers/net/ice/base/ice_ptp_hw.c | 22 ++++++++++++---------- drivers/net/ice/base/ice_type.h | 2 ++ 2 files changed, 14 insertions(+), 10 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 8ce803bfb3..427c16e1dd 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -1034,7 +1034,7 @@ ice_ptp_prep_phy_time_eth56g(struct ice_hw *hw, u32 time) */ phy_time = (u64)time << 32; - for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { + for (port = 0; port < hw->max_phy_port; port++) { if (!(hw->ena_lports & BIT(port))) continue; status = ice_ptp_prep_port_phy_time_eth56g(hw, port, @@ -1135,7 +1135,7 @@ ice_ptp_prep_phy_adj_eth56g(struct ice_hw *hw, s32 adj, bool lock_sbq) */ cycles = (s64)adj << 32; - for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { + for (port = 0; port < hw->max_phy_port; port++) { if (!(hw->ena_lports & BIT(port))) continue; @@ -1163,7 +1163,7 @@ ice_ptp_prep_phy_incval_eth56g(struct ice_hw *hw, u64 incval) int status; u8 port; - for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { + for (port = 0; port < hw->max_phy_port; port++) { if (!(hw->ena_lports & BIT(port))) continue; status = ice_write_40b_phy_reg_eth56g(hw, port, @@ -1225,7 +1225,7 @@ ice_ptp_prep_phy_adj_target_eth56g(struct ice_hw *hw, u32 target_time) int status; u8 port; - for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { + for (port = 0; port < hw->max_phy_port; port++) { if (!(hw->ena_lports & BIT(port))) continue; @@ -1412,7 +1412,7 @@ ice_ptp_port_cmd_eth56g(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, int status; u8 port; - for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { + for (port = 0; port < hw->max_phy_port; port++) { if (!(hw->ena_lports & BIT(port))) continue; @@ -1814,6 +1814,8 @@ ice_ptp_init_phy_cfg(struct ice_hw *hw) hw->phy_cfg = ICE_PHY_E810; else hw->phy_cfg = ICE_PHY_E822; + hw->phy_ports = ICE_NUM_EXTERNAL_PORTS; + hw->max_phy_port = ICE_NUM_EXTERNAL_PORTS; return 0; } @@ -2416,7 +2418,7 @@ int ice_ptp_set_vernier_wl(struct ice_hw *hw) { u8 port; - for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { + for (port = 0; port < hw->phy_ports; port++) { int status; status = ice_write_phy_reg_e822_lp(hw, port, P_REG_WL, @@ -2481,7 +2483,7 @@ ice_ptp_prep_phy_time_e822(struct ice_hw *hw, u32 time) */ phy_time = (u64)time << 32; - for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { + for (port = 0; port < hw->phy_ports; port++) { /* Tx case */ status = ice_write_64b_phy_reg_e822(hw, port, @@ -2590,7 +2592,7 @@ ice_ptp_prep_phy_adj_e822(struct ice_hw *hw, s32 adj, bool lock_sbq) else cycles = -(((s64)-adj) << 32); - for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { + for (port = 0; port < hw->phy_ports; port++) { int status; status = ice_ptp_prep_port_adj_e822(hw, port, cycles, @@ -2617,7 +2619,7 @@ ice_ptp_prep_phy_incval_e822(struct ice_hw *hw, u64 incval) int status; u8 port; - for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { + for (port = 0; port < hw->phy_ports; port++) { status = ice_write_40b_phy_reg_e822(hw, port, P_REG_TIMETUS_L, incval); if (status) @@ -2678,7 +2680,7 @@ ice_ptp_prep_phy_adj_target_e822(struct ice_hw *hw, u32 target_time) int status; u8 port; - for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { + for (port = 0; port < hw->phy_ports; port++) { /* Tx case */ /* No sub-nanoseconds data */ diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index 7a1471e474..48f892bfd3 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -1260,6 +1260,8 @@ struct ice_hw { u8 pf_id; /* device profile info */ enum ice_phy_cfg phy_cfg; + u8 phy_ports; + u8 max_phy_port; u8 logical_pf_id; u16 max_burst_size; /* driver sets this value */ -- 2.43.0