From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BC250A0A0E; Thu, 4 Feb 2021 09:06:42 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A61B624059F; Thu, 4 Feb 2021 09:06:42 +0100 (CET) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mails.dpdk.org (Postfix) with ESMTP id A1D5924059D for ; Thu, 4 Feb 2021 09:06:40 +0100 (CET) IronPort-SDR: KUfD7LtL4zf8AcDQzNiq494e9u82bGjy9BP/0QXJJtvUS2TZWnzBNJeB5PGAumPAwwjXSjgR52 foJAR/pXXr4Q== X-IronPort-AV: E=McAfee;i="6000,8403,9884"; a="160358547" X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="160358547" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 00:06:39 -0800 IronPort-SDR: ctjsyj0WSJpf8BE/HkOaeftk8n7v6Ns+HOGXaVUYOj1ZJXC3LFlamwFGzLl/nOxM3aWb1xYl9x Z9hGv5M3Ig5A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="372860593" Received: from fmsmsx603.amr.corp.intel.com ([10.18.126.83]) by orsmga002.jf.intel.com with ESMTP; 04 Feb 2021 00:06:38 -0800 Received: from shsmsx604.ccr.corp.intel.com (10.109.6.214) by fmsmsx603.amr.corp.intel.com (10.18.126.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Thu, 4 Feb 2021 00:06:38 -0800 Received: from shsmsx601.ccr.corp.intel.com (10.109.6.141) by SHSMSX604.ccr.corp.intel.com (10.109.6.214) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Thu, 4 Feb 2021 16:06:36 +0800 Received: from shsmsx601.ccr.corp.intel.com ([10.109.6.141]) by SHSMSX601.ccr.corp.intel.com ([10.109.6.141]) with mapi id 15.01.1713.004; Thu, 4 Feb 2021 16:06:36 +0800 From: "Zhang, Qi Z" To: "Zhang, Yuying" , "dev@dpdk.org" , "Wang, Haiyue" CC: "Fu, Qi" Thread-Topic: [PATCH v1] net/ice: fix QinQ switch rule input set mask Thread-Index: AQHW+r0fsopXZtj6qEC+mTwNw+hQEapHo7XQ Date: Thu, 4 Feb 2021 08:06:36 +0000 Message-ID: <42b57bd9f1624177bbce3379a95eca62@intel.com> References: <20210204060751.515216-1-yuying.zhang@intel.com> In-Reply-To: <20210204060751.515216-1-yuying.zhang@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.5.1.3 dlp-product: dlpe-windows x-originating-ip: [10.239.127.36] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v1] net/ice: fix QinQ switch rule input set mask X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Zhang, Yuying > Sent: Thursday, February 4, 2021 2:08 PM > To: dev@dpdk.org; Zhang, Qi Z ; Wang, Haiyue > > Cc: Fu, Qi ; Zhang, Yuying > Subject: [PATCH v1] net/ice: fix QinQ switch rule input set mask >=20 > QinQ switch rule doesn't support ethertype field match. > QinQ ethertype pattern should not be created. Change the input set mask t= o > fix the issue. >=20 > Fixes: bb3386f348dd ("net/ice: enable QinQ filter for switch") >=20 > Signed-off-by: Yuying Zhang Acked-by: Qi Zhang Applied to dpdk-next-net-intel. Thanks Qi