From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id D9E30806D for ; Tue, 16 Dec 2014 03:30:12 +0100 (CET) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP; 15 Dec 2014 18:29:55 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,862,1389772800"; d="scan'208";a="429415000" Received: from pgsmsx106.gar.corp.intel.com ([10.221.44.98]) by FMSMGA003.fm.intel.com with ESMTP; 15 Dec 2014 18:18:52 -0800 Received: from shsmsx103.ccr.corp.intel.com (10.239.110.14) by PGSMSX106.gar.corp.intel.com (10.221.44.98) with Microsoft SMTP Server (TLS) id 14.3.195.1; Tue, 16 Dec 2014 10:29:14 +0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.216]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.240]) with mapi id 14.03.0195.001; Tue, 16 Dec 2014 10:29:08 +0800 From: "Chen, Jing D" To: "Zhang, Helin" , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH v2] i40e: workaround for X710 performance issues Thread-Index: AQHQGDzGCZs8KVVBnU2xZEHRe3XxtZyReq2Q Date: Tue, 16 Dec 2014 02:29:06 +0000 Message-ID: <4341B239C0EFF9468EE453F9E9F4604D01630719@shsmsx102.ccr.corp.intel.com> References: <1418627370-28185-1-git-send-email-helin.zhang@intel.com> <1418630187-28917-1-git-send-email-helin.zhang@intel.com> In-Reply-To: <1418630187-28917-1-git-send-email-helin.zhang@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Cc: "Rowden, Aaron F" Subject: Re: [dpdk-dev] [PATCH v2] i40e: workaround for X710 performance issues X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 16 Dec 2014 02:30:13 -0000 Hi Helin, > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Helin Zhang > Sent: Monday, December 15, 2014 3:56 PM > To: dev@dpdk.org > Cc: Rowden, Aaron F > Subject: [dpdk-dev] [PATCH v2] i40e: workaround for X710 performance > issues >=20 > As the fixes of below performance issues on X710 may not be integrated > in latest version of firmware, a workaround in software PMD is needed. > It is to re-configure 3 specific registers after being initialized. > - Cannot achieve line rate on X710. packet size?=20 > - Performance reduction when promiscuous mode is disabled. You'd better add above descriptions in line with the code. > Note that this workaround can be removed if the fixes are integrated > in the firmware in future. >=20 I saw below code applied register setting in case it's 40G device. Can you = give more description on what device this patch would boost performance? Will 10G fiber interface benefit from the change? > Signed-off-by: Helin Zhang > --- > lib/librte_pmd_i40e/i40e_ethdev.c | 87 > +++++++++++++++++++++++++++++++++++++++ > 1 file changed, 87 insertions(+) >=20 > v2 changes: > * Added a compile error fix. >=20 > diff --git a/lib/librte_pmd_i40e/i40e_ethdev.c > b/lib/librte_pmd_i40e/i40e_ethdev.c > index 008d62c..82c072b 100644 > --- a/lib/librte_pmd_i40e/i40e_ethdev.c > +++ b/lib/librte_pmd_i40e/i40e_ethdev.c > @@ -198,6 +198,7 @@ static int i40e_dev_filter_ctrl(struct rte_eth_dev *d= ev, > enum rte_filter_type filter_type, > enum rte_filter_op filter_op, > void *arg); > +static void i40e_configure_registers(struct i40e_hw *hw); >=20 > /* Default hash key buffer for RSS */ > static uint32_t rss_key_default[I40E_PFQF_HKEY_MAX_INDEX + 1]; > @@ -443,6 +444,15 @@ eth_i40e_dev_init(__rte_unused struct eth_driver > *eth_drv, > /* Clear PXE mode */ > i40e_clear_pxe_mode(hw); >=20 > + /* > + * On X710, as old version of firmwares may have performance issues, > + * 3 registers need to be re-configured with new values. And the > latest > + * version of firmware may not contain the fixes, workaround in SW > + * driver is needed. This workaround can be removed when the fixes > are > + * integrated in firmware in future. > + */ > + i40e_configure_registers(hw); > + > /* Get hw capabilities */ > ret =3D i40e_get_cap(hw); > if (ret !=3D I40E_SUCCESS) { > @@ -5294,3 +5304,80 @@ i40e_pctype_to_flowtype(enum > i40e_filter_pctype pctype) >=20 > return flowtype_table[pctype]; > } > + > +static int > +i40e_debug_read_register(struct i40e_hw *hw, uint32_t addr, uint64_t > *val) > +{ > + struct i40e_aq_desc desc; > + struct i40e_aqc_debug_reg_read_write *cmd =3D > + (struct i40e_aqc_debug_reg_read_write > *)&desc.params.raw; > + enum i40e_status_code status; > + > + i40e_fill_default_direct_cmd_desc(&desc, > i40e_aqc_opc_debug_read_reg); > + cmd->address =3D rte_cpu_to_le_32(addr); > + status =3D i40e_asq_send_command(hw, &desc, NULL, 0, NULL); > + if (status < 0) > + return status; > + > + *val =3D ((uint64_t)(rte_le_to_cpu_32(cmd->value_high)) << > (CHAR_BIT * > + sizeof(uint32_t))) + rte_le_to_cpu_32(cmd- > >value_low); > + > + return status; > +} > + > +/* > + * On X710, as old version of firmwares may have performance issues, > + * 3 registers need to be re-configured with new values. And the latest > version > + * of firmware may not contain the fixes, workaround in SW driver is > needed. > + * This workaround can be removed when the fixes are integrated in > firmware in > + * future. > + */ > +static void > +i40e_configure_registers(struct i40e_hw *hw) > +{ > +#define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00 > +#define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08 > +#define I40E_GL_SWR_PM_UP_THR 0x269FBC > +#define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200 > +#define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200 > +#define I40E_GL_SWR_PM_UP_THR_VALUE 0x03030303 > + > + static const struct { > + uint32_t addr; > + uint64_t val; > + } reg_table[] =3D { > + {I40E_GL_SWR_PRI_JOIN_MAP_0, > I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE}, > + {I40E_GL_SWR_PRI_JOIN_MAP_2, > I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE}, > + {I40E_GL_SWR_PM_UP_THR, > I40E_GL_SWR_PM_UP_THR_VALUE}, > + }; > + uint64_t reg; > + uint32_t i; > + int ret; > + > + /* Below fix is for X710 only */ > + if (i40e_is_40G_device(hw->device_id)) > + return; > + > + for (i =3D 0; i < RTE_DIM(reg_table); i++) { > + ret =3D i40e_debug_read_register(hw, reg_table[i].addr, ®); > + if (ret < 0) { > + PMD_DRV_LOG(ERR, "Failed to read from 0x%x\n", > + reg_table[i].addr); > + break; > + } > + PMD_DRV_LOG(DEBUG, "Read from 0x%x: 0x%lx", > reg_table[i].addr, > + reg); PRIu64? > + if (reg =3D=3D reg_table[i].val) > + continue; > + > + ret =3D i40e_aq_debug_write_register(hw, reg_table[i].addr, > + reg_table[i].val, NULL); > + if (ret < 0) { > + PMD_DRV_LOG(ERR, "Failed to write 0x%lx to > 0x%x\n", > + reg_table[i].val, reg_table[i].addr); PRIu64? > + break; > + } > + PMD_DRV_LOG(DEBUG, "Write to 0x%x: 0x%lx", > reg_table[i].addr, > + reg_table[i].val); PRIu64? > + } > +} I saw some wrong code alignment above, but not sure how it looks like on=20 terminal, please double check. > -- > 1.8.1.4