From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id B9D0E9378 for ; Thu, 22 Oct 2015 08:52:39 +0200 (CEST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP; 21 Oct 2015 23:52:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,181,1444719600"; d="scan'208";a="816770217" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by fmsmga001.fm.intel.com with ESMTP; 21 Oct 2015 23:52:36 -0700 Received: from FMSMSX109.amr.corp.intel.com (10.18.116.9) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.248.2; Wed, 21 Oct 2015 23:52:36 -0700 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by fmsmsx109.amr.corp.intel.com (10.18.116.9) with Microsoft SMTP Server (TLS) id 14.3.248.2; Wed, 21 Oct 2015 23:52:35 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.253]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.204]) with mapi id 14.03.0248.002; Thu, 22 Oct 2015 14:52:29 +0800 From: "Chen, Jing D" To: "He, Shaopeng" , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH 2/5] fm10k: enable Rx queue interrupts for PF and VF Thread-Index: AQHQ91RTrfZzRcCWzEmtvGD7oh2OQZ53Of9w Date: Thu, 22 Oct 2015 06:52:28 +0000 Message-ID: <4341B239C0EFF9468EE453F9E9F4604D02AE1B12@shsmsx102.ccr.corp.intel.com> References: <1443159425-32502-1-git-send-email-shaopeng.he@intel.com> <1443159425-32502-3-git-send-email-shaopeng.he@intel.com> In-Reply-To: <1443159425-32502-3-git-send-email-shaopeng.he@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH 2/5] fm10k: enable Rx queue interrupts for PF and VF X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 22 Oct 2015 06:52:40 -0000 Hi, Best Regards, Mark > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Shaopeng He > Sent: Friday, September 25, 2015 1:37 PM > To: dev@dpdk.org > Subject: [dpdk-dev] [PATCH 2/5] fm10k: enable Rx queue interrupts for PF > and VF >=20 > The patch does below things for fm10k PF and VF: > - Setup NIC to generate MSI-X interrupts > - Set the RXINT register to map interrupt causes to vectors > - Implement interrupt enable/disable functions The description is too simple, can you help to extend? Besides that, there are complicated changes in this patch.=20 Can you help you split it to several smaller ones for better understanding? >=20 > Signed-off-by: Shaopeng He > --- > drivers/net/fm10k/fm10k_ethdev.c | 147 > +++++++++++++++++++++++++++++++++++++-- > 1 file changed, 140 insertions(+), 7 deletions(-) >=20 > diff --git a/drivers/net/fm10k/fm10k_ethdev.c > b/drivers/net/fm10k/fm10k_ethdev.c > index a82cd59..6648934 100644 > --- a/drivers/net/fm10k/fm10k_ethdev.c > +++ b/drivers/net/fm10k/fm10k_ethdev.c >=20 > static int > +fm10k_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t > queue_id) > +{ > + struct fm10k_hw *hw =3D FM10K_DEV_PRIVATE_TO_HW(dev->data- > >dev_private); > + > + /* Enable ITR */ > + if (hw->mac.type =3D=3D fm10k_mac_pf) > + FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(dev, queue_id)), > + FM10K_ITR_AUTOMASK | > FM10K_ITR_MASK_CLEAR); > + else > + FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(dev, queue_id)), > + FM10K_ITR_AUTOMASK | > FM10K_ITR_MASK_CLEAR); > + rte_intr_enable(&dev->pci_dev->intr_handle); > + return 0; > +} > + > +static int > +fm10k_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t > queue_id) > +{ > + struct fm10k_hw *hw =3D FM10K_DEV_PRIVATE_TO_HW(dev->data- > >dev_private); > + > + /* Disable ITR */ > + if (hw->mac.type =3D=3D fm10k_mac_pf) > + FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(dev, queue_id)), > + FM10K_ITR_MASK_SET); > + else > + FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(dev, queue_id)), > + FM10K_ITR_MASK_SET); In previous enable function, you'll use rte_intr_enable() to enable interru= pt, but=20 You needn't disable it in this function?=20 > + return 0; > +} > + > +static int > +fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev) > +{ > + struct fm10k_hw *hw =3D FM10K_DEV_PRIVATE_TO_HW(dev->data- > >dev_private); > + struct rte_intr_handle *intr_handle =3D &dev->pci_dev->intr_handle; > + uint32_t intr_vector, vec; > + uint16_t queue_id; > + int result =3D 0; > + > + /* fm10k needs interrupt for mailbox > + * so igb_uio is not supported for rx interrupt > + */ I guess you'll support both igb_uio and VFIO, RX interrupt mode only enable= d in case VFIO is used. I suggest you add more comments here for better understanding. > + if (!rte_intr_cap_multiple(intr_handle) || > + dev->data->dev_conf.intr_conf.rxq =3D=3D 0) > + return result; > + > + intr_vector =3D dev->data->nb_rx_queues; > + > + /* disable interrupt first */ > + rte_intr_disable(&dev->pci_dev->intr_handle); > + if (hw->mac.type =3D=3D fm10k_mac_pf) > + fm10k_dev_disable_intr_pf(dev); > + else > + fm10k_dev_disable_intr_vf(dev); > + > + if (rte_intr_efd_enable(intr_handle, intr_vector)) { > + PMD_INIT_LOG(ERR, "Failed to init event fd"); > + result =3D -EIO; > + } > + > + if (rte_intr_dp_is_en(intr_handle) && !result) { > + intr_handle->intr_vec =3D rte_zmalloc("intr_vec", > + dev->data->nb_rx_queues * sizeof(int), 0); > + if (intr_handle->intr_vec) { > + for (queue_id =3D 0, vec =3D RX_VEC_START; > + queue_id < dev->data- > >nb_rx_queues; > + queue_id++) { > + intr_handle->intr_vec[queue_id] =3D vec; > + if (vec < intr_handle->nb_efd - 1 + > RX_VEC_START) > + vec++; No "else" to handle exceptional case? > + } > + } else { > + PMD_INIT_LOG(ERR, "Failed to allocate %d > rx_queues" > + " intr_vec", dev->data->nb_rx_queues); > + result =3D -ENOMEM; > + } > + } > + > + if (hw->mac.type =3D=3D fm10k_mac_pf) > + fm10k_dev_enable_intr_pf(dev); > + else > + fm10k_dev_enable_intr_vf(dev); > + rte_intr_enable(&dev->pci_dev->intr_handle); > + hw->mac.ops.update_int_moderator(hw); > + return result; > +} > + > +static int > fm10k_dev_handle_fault(struct fm10k_hw *hw, uint32_t eicr) > { > struct fm10k_fault fault; > @@ -2050,6 +2181,8 @@ static const struct eth_dev_ops > fm10k_eth_dev_ops =3D { > .tx_queue_setup =3D fm10k_tx_queue_setup, > .tx_queue_release =3D fm10k_tx_queue_release, > .rx_descriptor_done =3D fm10k_dev_rx_descriptor_done, > + .rx_queue_intr_enable =3D fm10k_dev_rx_queue_intr_enable, > + .rx_queue_intr_disable =3D fm10k_dev_rx_queue_intr_disable, > .reta_update =3D fm10k_reta_update, > .reta_query =3D fm10k_reta_query, > .rss_hash_update =3D fm10k_rss_hash_update, > @@ -2060,7 +2193,7 @@ static int > eth_fm10k_dev_init(struct rte_eth_dev *dev) > { > struct fm10k_hw *hw =3D FM10K_DEV_PRIVATE_TO_HW(dev->data- > >dev_private); > - int diag; > + int diag, i; > struct fm10k_macvlan_filter_info *macvlan; >=20 > PMD_INIT_FUNC_TRACE(); > @@ -2177,7 +2310,7 @@ eth_fm10k_dev_init(struct rte_eth_dev *dev) > fm10k_dev_enable_intr_vf(dev); > } >=20 > - /* Enable uio intr after callback registered */ > + /* Enable intr after callback registered */ > rte_intr_enable(&(dev->pci_dev->intr_handle)); >=20 > hw->mac.ops.update_int_moderator(hw); > @@ -2185,7 +2318,6 @@ eth_fm10k_dev_init(struct rte_eth_dev *dev) > /* Make sure Switch Manager is ready before going forward. */ > if (hw->mac.type =3D=3D fm10k_mac_pf) { > int switch_ready =3D 0; > - int i; >=20 > for (i =3D 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) { > fm10k_mbx_lock(hw); > @@ -2291,7 +2423,8 @@ static struct eth_driver rte_pmd_fm10k =3D { > .pci_drv =3D { > .name =3D "rte_pmd_fm10k", > .id_table =3D pci_id_fm10k_map, > - .drv_flags =3D RTE_PCI_DRV_NEED_MAPPING | > RTE_PCI_DRV_DETACHABLE, > + .drv_flags =3D RTE_PCI_DRV_NEED_MAPPING | > RTE_PCI_DRV_INTR_LSC | > + RTE_PCI_DRV_DETACHABLE, > }, > .eth_dev_init =3D eth_fm10k_dev_init, > .eth_dev_uninit =3D eth_fm10k_dev_uninit, > -- > 1.9.3