From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B9011A0C41; Thu, 18 Nov 2021 13:25:43 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9590040687; Thu, 18 Nov 2021 13:25:43 +0100 (CET) Received: from out3-smtp.messagingengine.com (out3-smtp.messagingengine.com [66.111.4.27]) by mails.dpdk.org (Postfix) with ESMTP id C376C40395; Thu, 18 Nov 2021 13:25:41 +0100 (CET) Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 333565C0163; Thu, 18 Nov 2021 07:25:41 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Thu, 18 Nov 2021 07:25:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s=fm2; bh= jwP45s7W4K+VXN0lHdRf5zoFSV96ZLHiY+OlUYm7MzI=; b=sQek2xB59onYSsFD Md9l5DIhq1b3DSvY6CDG9maHgqM8+c7LC/s90SWIBCPcVFXlWkAYLlD4sd+JxZyK QvRq/qaNRi9BikjcP128amTzigsqiYNmMKDf5s1gUrAMV1H+tMubQb7mXvdqfUO3 R88WlV8ymcS2//htJ5jECKUXFaOdVq0D/naxhl3so3ktQpIhv3QhqVWNNhLsZ0SZ 7UuqUO+EGfuVvZN7VeeVoYOH6LBydw+3a3zY7cVFrU1k6/JK3xNdmI9t7Gucrg63 WUU8McvAT/Wv0CxQG9yIKGtTQOmfs1B0Fmsyo1kI51wtDOccFmNkMubcGAlTU14/ 7CgJ2Q== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; bh=jwP45s7W4K+VXN0lHdRf5zoFSV96ZLHiY+OlUYm7M zI=; b=I1ZEYvwaLS6Tm9cMyvMwGwkQkXmo1JhpSTPbTvlTI41Q9WLPdgkEy0U06 w2FT5EyeuysmfsgPdARmUy363yWZD+jnJn/reD1EDRDDZndLoYimcTdKuQRCS5Q5 xGNunoLP9ZVj749+tUy025Nx+B4ImTeghJdLkdKySFpzxtd3SZPaM/MH2Nyo62U/ WzZLwZb1W0SVsYAM1qHroNkmVthPf9bnBkdAgV+WYf3Hhi63D73AtMyo/fkmTPUH G0oe0n7Kgxb7vlOoMwaZEGuAYA/MNn7RKqLq9UNNvf6OZHz5T4ocv+/OVWGKM834 8AS66mRB4+tJ2qVnHpKlDNZhmt6bQ== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvuddrfeeigdefjecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvffufffkjghfggfgtgesthfuredttddtvdenucfhrhhomhepvfhhohhmrghs ucfoohhnjhgrlhhonhcuoehthhhomhgrshesmhhonhhjrghlohhnrdhnvghtqeenucggtf frrghtthgvrhhnpeffvdffjeeuteelfeeileduudeugfetjeelveefkeejfeeigeehteff vdekfeegudenucffohhmrghinhepughpughkrdhorhhgnecuvehluhhsthgvrhfuihiivg eptdenucfrrghrrghmpehmrghilhhfrhhomhepthhhohhmrghssehmohhnjhgrlhhonhdr nhgvth X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Thu, 18 Nov 2021 07:25:39 -0500 (EST) From: Thomas Monjalon To: Aman Kumar , David Marchand , "Song, Keesang" , techboard@dpdk.org Cc: dev@dpdk.org Subject: Re: [dpdk-dev] [PATCH] config/x86: add support for AMD platform Date: Thu, 18 Nov 2021 13:25:38 +0100 Message-ID: <4391381.llMs6SCV4p@thomas> In-Reply-To: <1902057.C4l9sbjloW@thomas> References: <20211102145253.413467-1-aman.kumar@vvdntech.in> <1902057.C4l9sbjloW@thomas> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org I request a techboard decision for this patch. 02/11/2021 20:04, Thomas Monjalon: > 02/11/2021 19:45, David Marchand: > > On Tue, Nov 2, 2021 at 3:53 PM Aman Kumar wrote: > > > > > > -Dcpu_instruction_set=znverX meson option can be used > > > to build dpdk for AMD platforms. Supported options are > > > znver1, znver2 and znver3. > > > > > > Signed-off-by: Aman Kumar > > > --- > > > dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64) > > > dpdk_conf.set('RTE_MAX_LCORE', 128) > > > dpdk_conf.set('RTE_MAX_NUMA_NODES', 32) > > > + > > > +# AMD platform support > > > +if get_option('cpu_instruction_set') == 'znver1' > > > + dpdk_conf.set('RTE_MAX_LCORE', 256) > > > +elif get_option('cpu_instruction_set') == 'znver2' > > > + dpdk_conf.set('RTE_MAX_LCORE', 512) > > > +elif get_option('cpu_instruction_set') == 'znver3' > > > + dpdk_conf.set('RTE_MAX_LCORE', 512) > > > +endif > > > > I already replied to a similar patch earlier in this release. > > https://inbox.dpdk.org/dev/CAJFAV8z-5amvEnr3mazkTqH-7SZX_C6EqCua6UdMXXHgrcmT6g@mail.gmail.com/ > > > > So repeating the same: do you actually _need_ more than 128 lcores in > > a single DPDK application? We did not receive an answer to this question. > Yes I forgot this previous discussion concluding that we should not increase > more than 128 threads. We had a discussion yesterday in techboard meeting. The consensus is that we didn't hear for real need of more than 128 threads, except for configuration usability convenience. Now looking again at the code, this is how it is defined: option('max_lcores', type: 'string', value: 'default', description: 'Set maximum number of cores/threads supported by EAL; "default" is different per-arch, "detect" detects the number of cores on the build machine.') config/x86/meson.build: dpdk_conf.set('RTE_MAX_LCORE', 128) config/ppc/meson.build: dpdk_conf.set('RTE_MAX_LCORE', 128) config/arm/meson.build: it goes from 4 to 1280! So I feel it is not fair to reject this AMD patch if we allow Arm to go beyond. Techboard, let's have a quick decision please for 21.11-rc4. > The --lcores syntax and David's work on rte_thread_register should unblock > most of use cases.