* [PATCH] net/mlx5: fix IPv6 DSCP offset in NT HWS API
@ 2025-09-30 7:28 Gavin Li
2025-11-12 8:58 ` Bing Zhao
2025-11-12 13:01 ` [PATCH V2] net/mlx5: fix IPv6 DSCP offset in HWS sync API Gavin Li
0 siblings, 2 replies; 5+ messages in thread
From: Gavin Li @ 2025-09-30 7:28 UTC (permalink / raw)
To: matan, viacheslavo, orika, thomas, Dariusz Sosnowski, Bing Zhao,
Suanming Mou, Minggang Li (Gavin)
Cc: dev, rasland, stable
The RTE action process in the HWS non-template API differs from the
process in SWS. The bit shift handling for IPv6 DSCP was not handled in
HWS, resulting in incorrect data in the field.
To resolve this, bit shift handling should be added to HWS.
Fixes: ec1e7a5ceb69 ("net/mlx5: update IPv6 traffic class modification")
Cc: stable@dpdk.org
Signed-off-by: Gavin Li <gavinl@nvidia.com>
---
drivers/net/mlx5/mlx5_flow.h | 5 +++++
drivers/net/mlx5/mlx5_flow_dv.c | 6 ------
drivers/net/mlx5/mlx5_flow_hw.c | 5 +++++
3 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index ff61706054..6ec853f018 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -3680,6 +3680,11 @@ void
mlx5_indirect_list_handles_release(struct rte_eth_dev *dev);
bool mlx5_flow_is_steering_disabled(void);
+static inline bool
+mlx5_dv_modify_ipv6_traffic_class_supported(struct mlx5_priv *priv)
+{
+ return priv->sh->phdev->config.ipv6_tc_fallback == MLX5_IPV6_TC_OK;
+}
#ifdef HAVE_MLX5_HWS_SUPPORT
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index bcce1597e2..517a5e530d 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -1638,12 +1638,6 @@ mlx5_modify_flex_item(const struct rte_eth_dev *dev,
}
}
-static inline bool
-mlx5_dv_modify_ipv6_traffic_class_supported(struct mlx5_priv *priv)
-{
- return priv->sh->phdev->config.ipv6_tc_fallback == MLX5_IPV6_TC_OK;
-}
-
void
mlx5_flow_field_id_to_modify_info
(const struct rte_flow_field_data *data,
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index 9a0aa1827e..628a47f2ce 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -1613,6 +1613,11 @@ flow_hw_modify_field_compile(struct rte_eth_dev *dev,
value = *(const uint8_t *)item.spec << 24;
value = rte_cpu_to_be_32(value);
item.spec = &value;
+ } else if (conf->dst.field == RTE_FLOW_FIELD_IPV6_DSCP &&
+ !(mask[0] & MLX5_IPV6_HDR_ECN_MASK) &&
+ mlx5_dv_modify_ipv6_traffic_class_supported(dev->data->dev_private)) {
+ value = *(const unaligned_uint32_t *)item.spec << MLX5_IPV6_HDR_DSCP_SHIFT;
+ item.spec = &value;
}
} else {
type = conf->operation == RTE_FLOW_MODIFY_SET ?
--
2.34.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH] net/mlx5: fix IPv6 DSCP offset in NT HWS API
2025-09-30 7:28 [PATCH] net/mlx5: fix IPv6 DSCP offset in NT HWS API Gavin Li
@ 2025-11-12 8:58 ` Bing Zhao
2025-11-12 9:09 ` Thomas Monjalon
2025-11-12 13:01 ` [PATCH V2] net/mlx5: fix IPv6 DSCP offset in HWS sync API Gavin Li
1 sibling, 1 reply; 5+ messages in thread
From: Bing Zhao @ 2025-11-12 8:58 UTC (permalink / raw)
To: Minggang(Gavin) Li, Matan Azrad, Slava Ovsiienko, Ori Kam,
NBU-Contact-Thomas Monjalon (EXTERNAL),
Dariusz Sosnowski, Suanming Mou
Cc: dev, Raslan Darawsheh, stable
Hi,
> -----Original Message-----
> From: Minggang(Gavin) Li <gavinl@nvidia.com>
> Sent: Tuesday, September 30, 2025 3:28 PM
> To: Matan Azrad <matan@nvidia.com>; Slava Ovsiienko
> <viacheslavo@nvidia.com>; Ori Kam <orika@nvidia.com>; NBU-Contact-Thomas
> Monjalon (EXTERNAL) <thomas@monjalon.net>; Dariusz Sosnowski
> <dsosnowski@nvidia.com>; Bing Zhao <bingz@nvidia.com>; Suanming Mou
> <suanmingm@nvidia.com>; Minggang(Gavin) Li <gavinl@nvidia.com>
> Cc: dev@dpdk.org; Raslan Darawsheh <rasland@nvidia.com>; stable@dpdk.org
> Subject: [PATCH] net/mlx5: fix IPv6 DSCP offset in NT HWS API
>
> The RTE action process in the HWS non-template API differs from the
> process in SWS. The bit shift handling for IPv6 DSCP was not handled in
> HWS, resulting in incorrect data in the field.
>
> To resolve this, bit shift handling should be added to HWS.
>
> Fixes: ec1e7a5ceb69 ("net/mlx5: update IPv6 traffic class modification")
> Cc: stable@dpdk.org
> Signed-off-by: Gavin Li <gavinl@nvidia.com>
> ---
> drivers/net/mlx5/mlx5_flow.h | 5 +++++
> drivers/net/mlx5/mlx5_flow_dv.c | 6 ------
> drivers/net/mlx5/mlx5_flow_hw.c | 5 +++++
> 3 files changed, 10 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
> index ff61706054..6ec853f018 100644
> --- a/drivers/net/mlx5/mlx5_flow.h
> +++ b/drivers/net/mlx5/mlx5_flow.h
> @@ -3680,6 +3680,11 @@ void
> mlx5_indirect_list_handles_release(struct rte_eth_dev *dev);
>
> bool mlx5_flow_is_steering_disabled(void);
> +static inline bool
> +mlx5_dv_modify_ipv6_traffic_class_supported(struct mlx5_priv *priv) {
> + return priv->sh->phdev->config.ipv6_tc_fallback ==
> MLX5_IPV6_TC_OK; }
>
> #ifdef HAVE_MLX5_HWS_SUPPORT
>
> diff --git a/drivers/net/mlx5/mlx5_flow_dv.c
> b/drivers/net/mlx5/mlx5_flow_dv.c index bcce1597e2..517a5e530d 100644
> --- a/drivers/net/mlx5/mlx5_flow_dv.c
> +++ b/drivers/net/mlx5/mlx5_flow_dv.c
> @@ -1638,12 +1638,6 @@ mlx5_modify_flex_item(const struct rte_eth_dev
> *dev,
> }
> }
>
> -static inline bool
> -mlx5_dv_modify_ipv6_traffic_class_supported(struct mlx5_priv *priv) -{
> - return priv->sh->phdev->config.ipv6_tc_fallback == MLX5_IPV6_TC_OK;
> -}
> -
> void
> mlx5_flow_field_id_to_modify_info
> (const struct rte_flow_field_data *data, diff --git
> a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index
> 9a0aa1827e..628a47f2ce 100644
> --- a/drivers/net/mlx5/mlx5_flow_hw.c
> +++ b/drivers/net/mlx5/mlx5_flow_hw.c
> @@ -1613,6 +1613,11 @@ flow_hw_modify_field_compile(struct rte_eth_dev
> *dev,
> value = *(const uint8_t *)item.spec << 24;
> value = rte_cpu_to_be_32(value);
> item.spec = &value;
> + } else if (conf->dst.field == RTE_FLOW_FIELD_IPV6_DSCP &&
> + !(mask[0] & MLX5_IPV6_HDR_ECN_MASK) &&
> + mlx5_dv_modify_ipv6_traffic_class_supported(dev-
> >data->dev_private)) {
> + value = *(const unaligned_uint32_t *)item.spec <<
> MLX5_IPV6_HDR_DSCP_SHIFT;
> + item.spec = &value;
> }
> } else {
> type = conf->operation == RTE_FLOW_MODIFY_SET ?
> --
> 2.34.1
Maybe the title can be changed to non-template API directly instead of NT HWS?
Acked-by: Bing Zhao <bingz@nvidia.com>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] net/mlx5: fix IPv6 DSCP offset in NT HWS API
2025-11-12 8:58 ` Bing Zhao
@ 2025-11-12 9:09 ` Thomas Monjalon
2025-11-12 12:47 ` Minggang(Gavin) Li
0 siblings, 1 reply; 5+ messages in thread
From: Thomas Monjalon @ 2025-11-12 9:09 UTC (permalink / raw)
To: Minggang(Gavin) Li, Bing Zhao
Cc: Matan Azrad, Slava Ovsiienko, Ori Kam, Dariusz Sosnowski,
Suanming Mou, dev, Raslan Darawsheh, stable, Maayan Kashani
12/11/2025 09:58, Bing Zhao:
> Maybe the title can be changed to non-template API directly instead of NT HWS?
No, the correct name is synchronous flow API with hardware steering.
You can shorten it as "HWS sync API".
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH] net/mlx5: fix IPv6 DSCP offset in NT HWS API
2025-11-12 9:09 ` Thomas Monjalon
@ 2025-11-12 12:47 ` Minggang(Gavin) Li
0 siblings, 0 replies; 5+ messages in thread
From: Minggang(Gavin) Li @ 2025-11-12 12:47 UTC (permalink / raw)
To: NBU-Contact-Thomas Monjalon (EXTERNAL), Bing Zhao
Cc: Matan Azrad, Slava Ovsiienko, Ori Kam, Dariusz Sosnowski,
Suanming Mou, dev, Raslan Darawsheh, stable, Maayan Kashani
> -----Original Message-----
> From: Thomas Monjalon <thomas@monjalon.net>
> Sent: Wednesday, November 12, 2025 5:10 PM
> To: Minggang(Gavin) Li <gavinl@nvidia.com>; Bing Zhao <bingz@nvidia.com>
> Cc: Matan Azrad <matan@nvidia.com>; Slava Ovsiienko
> <viacheslavo@nvidia.com>; Ori Kam <orika@nvidia.com>; Dariusz Sosnowski
> <dsosnowski@nvidia.com>; Suanming Mou <suanmingm@nvidia.com>;
> dev@dpdk.org; Raslan Darawsheh <rasland@nvidia.com>; stable@dpdk.org;
> Maayan Kashani <mkashani@nvidia.com>
> Subject: Re: [PATCH] net/mlx5: fix IPv6 DSCP offset in NT HWS API
>
> 12/11/2025 09:58, Bing Zhao:
> > Maybe the title can be changed to non-template API directly instead of NT
> HWS?
>
> No, the correct name is synchronous flow API with hardware steering.
> You can shorten it as "HWS sync API".
ACK
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH V2] net/mlx5: fix IPv6 DSCP offset in HWS sync API
2025-09-30 7:28 [PATCH] net/mlx5: fix IPv6 DSCP offset in NT HWS API Gavin Li
2025-11-12 8:58 ` Bing Zhao
@ 2025-11-12 13:01 ` Gavin Li
1 sibling, 0 replies; 5+ messages in thread
From: Gavin Li @ 2025-11-12 13:01 UTC (permalink / raw)
To: dev, dsosnowski, viacheslavo, orika, suanmingm, matan
Cc: jiaweiw, rasland, stable, Bing Zhao
The RTE action process in synchronous flow API with hardware steering
differs from the process in SWS. The bit shift handling for IPv6 DSCP was
not handled in HWS, resulting in incorrect data in the field.
To resolve this, bit shift handling should be added to HWS.
Fixes: ec1e7a5ceb69 ("net/mlx5: update IPv6 traffic class modification")
Cc: stable@dpdk.org
Signed-off-by: Gavin Li <gavinl@nvidia.com>
Acked-by: Bing Zhao <bingz@nvidia.com>
---
drivers/net/mlx5/mlx5_flow.h | 5 +++++
drivers/net/mlx5/mlx5_flow_dv.c | 6 ------
drivers/net/mlx5/mlx5_flow_hw.c | 5 +++++
3 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index e8b298dd1d..fafcdccbed 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -3715,6 +3715,11 @@ void
mlx5_indirect_list_handles_release(struct rte_eth_dev *dev);
bool mlx5_flow_is_steering_disabled(void);
+static inline bool
+mlx5_dv_modify_ipv6_traffic_class_supported(struct mlx5_priv *priv)
+{
+ return priv->sh->phdev->config.ipv6_tc_fallback == MLX5_IPV6_TC_OK;
+}
#ifdef HAVE_MLX5_HWS_SUPPORT
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 95ca57e8c4..83046418c4 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -1638,12 +1638,6 @@ mlx5_modify_flex_item(const struct rte_eth_dev *dev,
}
}
-static inline bool
-mlx5_dv_modify_ipv6_traffic_class_supported(struct mlx5_priv *priv)
-{
- return priv->sh->phdev->config.ipv6_tc_fallback == MLX5_IPV6_TC_OK;
-}
-
void
mlx5_flow_field_id_to_modify_info
(const struct rte_flow_field_data *data,
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index 208f50fbfd..d3d2272338 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -1629,6 +1629,11 @@ flow_hw_modify_field_compile(struct rte_eth_dev *dev,
value = *(const uint8_t *)item.spec << 24;
value = rte_cpu_to_be_32(value);
item.spec = &value;
+ } else if (conf->dst.field == RTE_FLOW_FIELD_IPV6_DSCP &&
+ !(mask[0] & MLX5_IPV6_HDR_ECN_MASK) &&
+ mlx5_dv_modify_ipv6_traffic_class_supported(dev->data->dev_private)) {
+ value = *(const unaligned_uint32_t *)item.spec << MLX5_IPV6_HDR_DSCP_SHIFT;
+ item.spec = &value;
}
} else {
type = conf->operation == RTE_FLOW_MODIFY_SET ?
--
2.34.1
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2025-11-12 13:02 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2025-09-30 7:28 [PATCH] net/mlx5: fix IPv6 DSCP offset in NT HWS API Gavin Li
2025-11-12 8:58 ` Bing Zhao
2025-11-12 9:09 ` Thomas Monjalon
2025-11-12 12:47 ` Minggang(Gavin) Li
2025-11-12 13:01 ` [PATCH V2] net/mlx5: fix IPv6 DSCP offset in HWS sync API Gavin Li
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