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The holes are >> due to alignment requirement. >> >> For struct lcore_rx_queue, there is no need to make every element >> of this type to be cache line aligned, because the data is not >> shared between cores. >> >> Member len of struct mbuf_table can be moved out. So data can be >> packed and there will be no need to load an extra cache line when >> mbuf table is empty. >> >> The change showed slight performance improvement on N1SDP platform. >> >> Suggested-by: Honnappa Nagarahalli >> >> Signed-off-by: Ruifeng Wang > This change alone is OK in the octeontx2 platform.(No difference in performance) > combining with 3/4 shows some regression. Probably is due to prefetch > or 128B cache line tuning specifics. We checked it on Layerscape LS2088A platform. No difference for 1-2 core case. However observing ~2% regression for 4-8 cores. Regards, Hemant