From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id D5739A0598; Fri, 10 Apr 2020 19:21:04 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id BC0DB1D600; Fri, 10 Apr 2020 19:21:03 +0200 (CEST) Received: from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com [67.231.154.164]) by dpdk.org (Postfix) with ESMTP id 3C6DA1D5FB for ; Fri, 10 Apr 2020 19:21:02 +0200 (CEST) Received: from mx1-us1.ppe-hosted.com (unknown [10.110.50.137]) by dispatch1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id F1BCC200D0; Fri, 10 Apr 2020 17:21:00 +0000 (UTC) Received: from us4-mdac16-57.at1.mdlocal (unknown [10.110.50.149]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id EFEFC6009B; Fri, 10 Apr 2020 17:21:00 +0000 (UTC) X-Virus-Scanned: Proofpoint Essentials engine Received: from mx1-us1.ppe-hosted.com (unknown [10.110.50.12]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id 7217522007A; Fri, 10 Apr 2020 17:21:00 +0000 (UTC) Received: from webmail.solarflare.com (uk.solarflare.com [193.34.186.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id C33E44006C; Fri, 10 Apr 2020 17:20:58 +0000 (UTC) Received: from [127.0.0.27] (10.17.10.39) by ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 10 Apr 2020 18:20:45 +0100 To: Gavin Hu , CC: , , , , , , , , , , , , , , , References: <20200213123854.203566-1-gavin.hu@arm.com> <20200410164127.54229-1-gavin.hu@arm.com> From: Andrew Rybchenko Message-ID: <459f34b7-9e40-4110-3701-087261b223cd@solarflare.com> Date: Fri, 10 Apr 2020 20:20:36 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.6.0 MIME-Version: 1.0 In-Reply-To: <20200410164127.54229-1-gavin.hu@arm.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.17.10.39] X-ClientProxiedBy: ocex03.SolarFlarecom.com (10.20.40.36) To ukex01.SolarFlarecom.com (10.17.10.4) X-TM-AS-Product-Ver: SMEX-12.5.0.1300-8.5.1020-25346.003 X-TM-AS-Result: No-10.628300-8.000000-10 X-TMASE-MatchedRID: QfHZjzml1E/mLzc6AOD8DfHkpkyUphL93TijyM9Pm06YeMTPaAHLLW2r DqsRwTo3cJSEbD//zarch1K+AYIzY2swYILDF+F3aFAKyqG5M2JGOo6Qo+alrgVQtPavvwzPAEH N8UFHS9gWfK1X5E6qeb/oKq2v57PDofaD2zI+zzxl1tleYYUuJ7pFPlwWnnjKkaEC8FJraL+Jvf ShQlCoH6UnIuj41849u0UASV1c9SrMdO/aI0cjokiQO8rG9a3+AZn/4A9db2TtcZYGmyEIb6PFj JEFr+olA9Mriq0CDAgBi3kqJOK62QtuKBGekqUpI/NGWt0UYPAqTEFhSrSoLEPGLmYKPbuQotU/ uDmkVQenpSd47WAiTHxK8ruA57Zr X-TM-AS-User-Approved-Sender: Yes X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--10.628300-8.000000 X-TMASE-Version: SMEX-12.5.0.1300-8.5.1020-25346.003 X-MDID: 1586539260-2EJnqVE6FxTj Subject: Re: [dpdk-dev] [PATCH RFC v2 0/7] introduce new barrier class and use it for mlx5 PMD X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 4/10/20 7:41 PM, Gavin Hu wrote: > To order writes to various memory types, 'sfence' is required for x86, > and 'dmb oshst' is required for aarch64. > > But within DPDK, there is no abstracted barriers covers this > combination: sfence(x86)/dmb(aarch64). > > So introduce a new barrier class - rte_dma_*mb for this combination, > > Doorbell rings are typical use cases of this new barrier class, which > requires something ready in the memory before letting HW aware. > > As a note, rte_io_wmb and rte_cio_wmb are compiler barriers for x86, while > rte_wmb is 'dsb' for aarch64. As far as I can see rte_cio_wmb() is exactly definition of the barrier to be used for doorbells. Am I missing something? May be it is just a bug in rte_cio_wmb() on x86? > In the joint preliminary testing between Arm and Ampere, 8%~13% > performance boost was measured. > > As there is no functionality changes, it will not impact x86. > > Gavin Hu (6): > eal: introduce new class of barriers for DMA use cases > net/mlx5: dmb for immediate doorbell ring on aarch64 > net/mlx5: relax barrier to order UAR writes on aarch64 > net/mlx5: relax barrier for aarch64 > net/mlx5: add descriptive comment for a barrier > doc: clarify one configuration in mlx5 guide > > Phil Yang (1): > net/mlx5: relax ordering for multi-packet RQ buffer refcnt > > doc/guides/nics/mlx5.rst | 6 ++-- > drivers/net/mlx5/mlx5_rxq.c | 2 +- > drivers/net/mlx5/mlx5_rxtx.c | 16 ++++++----- > drivers/net/mlx5/mlx5_rxtx.h | 14 ++++++---- > lib/librte_eal/arm/include/rte_atomic_32.h | 6 ++++ > lib/librte_eal/arm/include/rte_atomic_64.h | 6 ++++ > lib/librte_eal/include/generic/rte_atomic.h | 31 +++++++++++++++++++++ > lib/librte_eal/ppc/include/rte_atomic.h | 6 ++++ > lib/librte_eal/x86/include/rte_atomic.h | 6 ++++ > 9 files changed, 78 insertions(+), 15 deletions(-) >