From: Thomas Monjalon <thomas@monjalon.net>
To: Pavan Nikhilesh <pbhagavatula@marvell.com>
Cc: dev@dpdk.org, Jerin Jacob <jerinj@marvell.com>,
Nithin Dabilpuram <ndabilpuram@marvell.com>,
Vamsi Attunuru <vattunuru@marvell.com>,
Jerin Jacob <jerinjacobk@gmail.com>
Subject: Re: [dpdk-dev] [PATCH v2] mempool/octeontx2: optimize for L1D cache architecture
Date: Sun, 16 Feb 2020 21:33:17 +0100 [thread overview]
Message-ID: <47936875.zMMnDpVMM9@xps> (raw)
In-Reply-To: <CALBAE1O-BQoHh3dio7EsSKxq5b_1Rvx_V+=p32cY=AQQh9=wwA@mail.gmail.com>
01/02/2020 12:51, Jerin Jacob:
> On Fri, Jan 31, 2020 at 10:53 PM <pbhagavatula@marvell.com> wrote:
> >
> > From: Pavan Nikhilesh <pbhagavatula@marvell.com>
> >
> > OCTEON TX2 has 8 sets, 41 ways L1D cache, VA<9:7> bits dictate
> > the set selection.
> > Add additional padding to ensure that the element size always
> > occupies odd number of cachelines to ensure even distribution
> > of elements among L1D cache sets.
> >
> > Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> > Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
> > Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
> > Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> > ---
> > v2 Changes:
> > ----------
> > - Fix 32bit build break.
>
> Acked-by: Jerin Jacob <jerinj@marvell.com>
>
> Delegated the patch to Thomas as it has come through the main tree.
Applied, thanks
prev parent reply other threads:[~2020-02-16 20:33 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-31 12:50 [dpdk-dev] [PATCH] " pbhagavatula
2020-01-31 15:55 ` Jerin Jacob
2020-01-31 17:23 ` [dpdk-dev] [PATCH v2] " pbhagavatula
2020-02-01 11:51 ` Jerin Jacob
2020-02-16 20:33 ` Thomas Monjalon [this message]
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