From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id BE10FA0613 for ; Fri, 30 Aug 2019 08:18:03 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 91E911E566; Fri, 30 Aug 2019 08:18:03 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 6E0261E557 for ; Fri, 30 Aug 2019 08:18:01 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Aug 2019 23:18:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,446,1559545200"; d="scan'208";a="332761141" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by orsmga004.jf.intel.com with ESMTP; 29 Aug 2019 23:18:00 -0700 Received: from fmsmsx156.amr.corp.intel.com (10.18.116.74) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 29 Aug 2019 23:18:00 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by fmsmsx156.amr.corp.intel.com (10.18.116.74) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 29 Aug 2019 23:17:59 -0700 Received: from shsmsx106.ccr.corp.intel.com ([169.254.10.204]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.62]) with mapi id 14.03.0439.000; Fri, 30 Aug 2019 14:17:58 +0800 From: "Rong, Leyi" To: "Zhang, Qi Z" , "Ye, Xiaolong" , "Wang, Haiyue" , "Lu, Wenzhuo" CC: "dev@dpdk.org" Thread-Topic: [PATCH v2 6/6] net/ice: switch to Rx flexible descriptor in AVX path Thread-Index: AQHVXkCquUmNYSs54Ui0pxArc76CeKcSQT8AgAD2KiA= Date: Fri, 30 Aug 2019 06:17:58 +0000 Message-ID: <47ACC7359E973C41ACB0C2477632BC725228E7AF@SHSMSX106.ccr.corp.intel.com> References: <20190829023421.112551-2-leyi.rong@intel.com> <20190829080441.12602-1-leyi.rong@intel.com> <20190829080441.12602-7-leyi.rong@intel.com> <039ED4275CED7440929022BC67E7061153D8671C@SHSMSX105.ccr.corp.intel.com> In-Reply-To: <039ED4275CED7440929022BC67E7061153D8671C@SHSMSX105.ccr.corp.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2 6/6] net/ice: switch to Rx flexible descriptor in AVX path X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Zhang, Qi Z > Sent: Friday, August 30, 2019 7:32 AM > To: Rong, Leyi ; Ye, Xiaolong ; > Wang, Haiyue ; Lu, Wenzhuo > Cc: dev@dpdk.org > Subject: RE: [PATCH v2 6/6] net/ice: switch to Rx flexible descriptor in = AVX path >=20 >=20 > > * take the two sets of status bits and merge to one @@ - > 450,20 > > +452,22 @@ _ice_recv_raw_pkts_vec_avx2(struct ice_rx_queue *rxq, > > +struct > > rte_mbuf **rx_pkts, > > /* get only flag/error bits we want */ > > const __m256i flag_bits =3D > > _mm256_and_si256(status0_7, flags_mask); > > - /* set vlan and rss flags */ > > - const __m256i vlan_flags =3D > > - _mm256_shuffle_epi8(vlan_flags_shuf, flag_bits); > > - const __m256i rss_flags =3D > > - _mm256_shuffle_epi8(rss_flags_shuf, > > - _mm256_srli_epi32(flag_bits, 11)); > > /** > > * l3_l4_error flags, shuffle, then shift to correct adjustment > > * of flags in flags_shuf, and finally mask out extra bits > > */ > > __m256i l3_l4_flags =3D _mm256_shuffle_epi8(l3_l4_flags_shuf, > > - _mm256_srli_epi32(flag_bits, 22)); > > + _mm256_srli_epi32(flag_bits, 4)); > > l3_l4_flags =3D _mm256_slli_epi32(l3_l4_flags, 1); > > l3_l4_flags =3D _mm256_and_si256(l3_l4_flags, cksum_mask); > > + /* set rss and vlan flags */ > > + const __m256i rss_vlan_flag_bits =3D > > + _mm256_srli_epi32(flag_bits, 12); > > + const __m256i rss_flags =3D > > + _mm256_shuffle_epi8(rss_flags_shuf, > rss_vlan_flag_bits); > > + const __m256i vlan_flags =3D > > + _mm256_shuffle_epi8(vlan_flags_shuf, > > + rss_vlan_flag_bits); >=20 > Seems we can "or" rss_flags_shuf and vlan_flags_shuf, so just need to do = one > shuffle here to save some CPU cycles? >=20 That's make sense literally, will do some benchmarking test for this adjust= ment:). > > > > /* merge flags */ > > const __m256i mbuf_flags =3D _mm256_or_si256(l3_l4_flags, > > -- > > 2.17.1