From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C6038A0567; Sun, 26 Jun 2022 23:23:03 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6E8DF41141; Sun, 26 Jun 2022 23:23:03 +0200 (CEST) Received: from out3-smtp.messagingengine.com (out3-smtp.messagingengine.com [66.111.4.27]) by mails.dpdk.org (Postfix) with ESMTP id 2D4DB40E50; Sun, 26 Jun 2022 23:23:02 +0200 (CEST) Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.nyi.internal (Postfix) with ESMTP id DBA1A5C0154; Sun, 26 Jun 2022 17:23:00 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute5.internal (MEProxy); Sun, 26 Jun 2022 17:23:00 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm2; t=1656278580; x= 1656364980; bh=nWN0RIIrhlK7esMQFmb781K+WapS5Fp83OcEn8BUMD4=; b=M EscaJPa+5BMY9yj8svrXtL8DlQKGV23U9UVgRhs/z4CM7uzmCQn5Qty6N/9bbesE FirQLHqIGSuYRu2FntOA/4p2g6G/vNOcW9upPKWAoZt1JqizhjYwoPlib9EnFx3n gPGBnR622vieNnidPtm4mZZCwAF+ufUOncL/0GedVbfyEZ8TiXD7cO+v4mjrg5Qg wJG0aMFliW4ur/n6lr7mspcLDQxZoz57l8RaaxQ4EwMp+syQCwtmy49+eFwI5mJq HyiJTQ5/kSnSbKT0oX7D4y7J8oMh0KsSMM4RHtXIIbQ9vV+gCWac1QZOC3rb+did zyDFlgnhEXZBA7FzhfofA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm2; t=1656278580; x= 1656364980; bh=nWN0RIIrhlK7esMQFmb781K+WapS5Fp83OcEn8BUMD4=; b=Y wAW6tXP64Ty3VgrY1+aUrreVeeh3iSY2pSzHV54w/QyjVFuuOzCtpnqOssC0W9dY sVGdvfCOT9TN53W/d7bg/gBQUJty7WZg9iEu9VO4Q0caC1IkEqUveWZFFW6kCSHR O1D/QxJ+mU7W6CHe58hDfeHuE276Gj+NKKXSA9NN6lB+Spnp/Rxs9KOBT2v/GEmi 8B7xx3L8qvi4wWH1m27Ht3jsslQHkDmnA6CuK/5r/uIO6ErNQsSm7CO3JhPYugJ0 yd6AGVHi8dPbgsW7N6zqcikjfirNCJehtYwfyb3S6Sbc65Y2WUnlN6YQrfgkB30l 8GZrYulCYiq59bQx2CiOg== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrudegfedgudeivdcutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfgh necuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd enucfjughrpefhvfevufffkfgjfhgggfgtsehtufertddttddvnecuhfhrohhmpefvhhho mhgrshcuofhonhhjrghlohhnuceothhhohhmrghssehmohhnjhgrlhhonhdrnhgvtheqne cuggftrfgrthhtvghrnheptdejieeifeehtdffgfdvleetueeffeehueejgfeuteeftddt ieekgfekudehtdfgnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilh hfrhhomhepthhhohhmrghssehmohhnjhgrlhhonhdrnhgvth X-ME-Proxy: Feedback-ID: i47234305:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Sun, 26 Jun 2022 17:23:00 -0400 (EDT) From: Thomas Monjalon To: Raja Zidane Cc: dev@dpdk.org, matan@nvidia.com, stable@dpdk.org Subject: Re: [PATCH] examples/link_status_interrupt: fix stats refresh rate Date: Sun, 26 Jun 2022 23:22:59 +0200 Message-ID: <4816203.0YcMNavOfZ@thomas> In-Reply-To: <20220530093702.11745-1-rzidane@nvidia.com> References: <20220530093702.11745-1-rzidane@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org 30/05/2022 11:37, Raja Zidane: > TIMER_MILLISECOND is defined as the number of cpu cycles per millisecond, > current definition is correct for cores with frequency of 2GHZ, for cores > with different frequency, it caused different periods between refresh, > (i.e. the definition is about 14ms on ARM cores). > > Use dpdk API to get CPU frequency, to define TIMER_MILLISECOND. > > Fixes: af75078fece3 ("first public release") > Cc: stable@dpdk.org > > Signed-off-by: Raja Zidane > Acked-by: Matan Azrad > --- > --- a/examples/link_status_interrupt/main.c > +++ b/examples/link_status_interrupt/main.c > /* A tsc-based timer responsible for triggering statistics printout */ > -#define TIMER_MILLISECOND 2000000ULL /* around 1ms at 2 Ghz */ > +#define TIMER_MILLISECOND (rte_get_tsc_hz() / 1000) It is preferred to use rte_get_timer_hz(). > #define MAX_TIMER_PERIOD 86400 /* 1 day max */ > -static int64_t timer_period = 10 * TIMER_MILLISECOND * 1000; /* default period is 10 seconds */ > +#define DEFAULT_TIMER_PERIOD 10UL /* default period is 10 seconds */ > +static int64_t timer_period; [...] > + timer_period = DEFAULT_TIMER_PERIOD; After a quick look, it seems we are missing the operation * TIMER_MILLISECOND * 1000 Isn't it?