From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B262F4404F; Wed, 12 Jun 2024 17:11:59 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6DB9F42D6A; Wed, 12 Jun 2024 17:04:35 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by mails.dpdk.org (Postfix) with ESMTP id 04AB14111B for ; Wed, 12 Jun 2024 17:04:29 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718204670; x=1749740670; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=A/GNDGBBJ6/2OpVCUW23xTsCfBCLu0FWTDqYi8UdViE=; b=DjxHHB4bHs8paH6p0F2l86+w0KkLolsasOU3QmD2gxcAMV5BzruDchDf mSKtraliZGb3vPPLDywYbC+xrw5A74TCWEEc79vLcp/4c0H9iKjIwsudf bhbVi6nGaz7KJ2sClUX3G8RRtQRjhj4DDokz0YfrEyGXjDfiKm9ZONPrH ImR4RO0scm+aU/Fx2Hj0E/8b3RahbUwz4L0xngKcj7ssCwa3mUrzp/Pp9 KH/o1RIyHQW84ukwQ63Bnmrlqm9Mvke9Ym2xdbniuAIQhF2KUprhw+wta NXnsmsXHtNRKVV/4MBX6dY23P6CFk+JmrfkNp5KvAK/lUeqD+y6GJJqnM Q==; X-CSE-ConnectionGUID: arvJU2vkSU2le4G43Q8xHg== X-CSE-MsgGUID: Scl7AoCpQEWZyWSFIrTOWA== X-IronPort-AV: E=McAfee;i="6700,10204,11101"; a="32459440" X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="32459440" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2024 08:04:28 -0700 X-CSE-ConnectionGUID: nTpP8puZR9+d60bnZQPd2g== X-CSE-MsgGUID: 9MwjevY1S6KDDmOHYBjkcg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="39925178" Received: from silpixa00401119.ir.intel.com ([10.55.129.167]) by orviesa009.jf.intel.com with ESMTP; 12 Jun 2024 08:04:27 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Ian Stokes , bruce.richardson@intel.com, Jesse Brandeburg Subject: [PATCH v2 044/148] net/ice/base: fix sign-extension Date: Wed, 12 Jun 2024 16:00:38 +0100 Message-ID: <495ae7e95c6ac38b6d4080ca229b407a4ef7ff16.1718204528.git.anatoly.burakov@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: <20240430154014.1026-1-ian.stokes@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Ian Stokes Fix a static analysis warning where if the 16-bit value in mask has the high-bit set, it will be sign extended by the shift left (which converts it to a signed integer). Avoid this by casting to a u32 to make sure the conversion happens before the shift and that it stays unsigned. Signed-off-by: Jesse Brandeburg Signed-off-by: Ian Stokes --- drivers/net/ice/base/ice_flex_pipe.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c index e06dbb0885..413b6f8ece 100644 --- a/drivers/net/ice/base/ice_flex_pipe.c +++ b/drivers/net/ice/base/ice_flex_pipe.c @@ -1534,16 +1534,14 @@ ice_write_prof_mask_reg(struct ice_hw *hw, enum ice_block blk, u16 mask_idx, switch (blk) { case ICE_BLK_RSS: offset = GLQF_HMASK(mask_idx); - val = (idx << GLQF_HMASK_MSK_INDEX_S) & - GLQF_HMASK_MSK_INDEX_M; - val |= (mask << GLQF_HMASK_MASK_S) & GLQF_HMASK_MASK_M; + val = (idx << GLQF_HMASK_MSK_INDEX_S) & GLQF_HMASK_MSK_INDEX_M; + val |= ((u32)mask << GLQF_HMASK_MASK_S) & GLQF_HMASK_MASK_M; break; case ICE_BLK_FD: offset = GLQF_FDMASK(mask_idx); val = (idx << GLQF_FDMASK_MSK_INDEX_S) & GLQF_FDMASK_MSK_INDEX_M; - val |= (mask << GLQF_FDMASK_MASK_S) & - GLQF_FDMASK_MASK_M; + val |= ((u32)mask << GLQF_FDMASK_MASK_S) & GLQF_FDMASK_MASK_M; break; default: ice_debug(hw, ICE_DBG_PKG, "No profile masks for block %d\n", -- 2.43.0