From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id BEA462BE1; Wed, 11 Oct 2017 09:13:35 +0200 (CEST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Oct 2017 00:13:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.43,360,1503385200"; d="scan'208";a="1204556277" Received: from kmsmsx152.gar.corp.intel.com ([172.21.73.87]) by fmsmga001.fm.intel.com with ESMTP; 11 Oct 2017 00:13:34 -0700 Received: from pgsmsx106.gar.corp.intel.com ([169.254.9.199]) by KMSMSX152.gar.corp.intel.com ([169.254.11.206]) with mapi id 14.03.0319.002; Wed, 11 Oct 2017 15:10:25 +0800 From: "Dai, Wei" To: "Ma, Jianwei" , "Lu, Wenzhuo" , "Ananyev, Konstantin" CC: "dev@dpdk.org" , "stable@dpdk.org" Thread-Topic: [PATCH] net/ixgbe: fix Rx queue interrupt mapping in VF Thread-Index: AQHTMfuMdNJMG1x4iE2lFP2vYm+CTqLcip5ggABXrCCAAXllwA== Date: Wed, 11 Oct 2017 07:10:24 +0000 Message-ID: <49759EB36A64CF4892C1AFEC9231E8D650BA0285@PGSMSX106.gar.corp.intel.com> References: <1505902693-51337-1-git-send-email-wei.dai@intel.com> <49759EB36A64CF4892C1AFEC9231E8D650B9FC8B@PGSMSX106.gar.corp.intel.com> In-Reply-To: Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiOTRmZWM2ZGEtMTkzYy00MjU4LWIxZWItZDE1MDkzNzhmOWQyIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE2LjUuOS4zIiwiVHJ1c3RlZExhYmVsSGFzaCI6ImVNeFBkelwvUkh6Q1hxaXJOTyttNTI4TU1pM05rY2JFdHQrWVkrY1FYU3pNPSJ9 x-ctpclassification: CTP_IC dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [172.30.20.206] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH] net/ixgbe: fix Rx queue interrupt mapping in VF X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Oct 2017 07:13:36 -0000 I look through from web browser and not find following mail from Jianwei Ma= Hope this can add his test result in the mail list to community. > -----Original Message----- > From: Ma, Jianwei > Sent: Tuesday, October 10, 2017 4:48 PM > To: Dai, Wei ; Lu, Wenzhuo ; > Ananyev, Konstantin > Cc: dev@dpdk.org; stable@dpdk.org > Subject: RE: [PATCH] net/ixgbe: fix Rx queue interrupt mapping in VF >=20 > Verified with l3fwd-power. It worked well with this patch plus > http://dpdk.org/dev/patchwork/patch/29221/ "[dpdk-dev,v2] net/ixgbe: > fix VFIO interrupt mapping in VF" >=20 > -----Original Message----- > From: Dai, Wei > Sent: Tuesday, October 10, 2017 11:26 > To: Lu, Wenzhuo ; Ananyev, Konstantin > ; Ma, Jianwei > Cc: dev@dpdk.org; stable@dpdk.org > Subject: RE: [PATCH] net/ixgbe: fix Rx queue interrupt mapping in VF >=20 > Hi, Jianwei > How about your test result ? >=20 > Hi, Wenzhuo > Would you please review this patch ? >=20 > Thanks a lot ! >=20 > > -----Original Message----- > > From: Dai, Wei > > Sent: Wednesday, September 20, 2017 6:18 PM > > To: Lu, Wenzhuo ; Ananyev, Konstantin > > > > Cc: dev@dpdk.org; Dai, Wei ; stable@dpdk.org > > Subject: [PATCH] net/ixgbe: fix Rx queue interrupt mapping in VF > > > > When a VF port is bound to VFIO-PCI, miscellaneous interrupt is mapped > > to MSI-X vector 0 and Rx queues interrupt are mapped to other vectors > > in vfio_enable_msix( ). To simplify implementation, all VFIO-PCI bound > > ixgbe VF Rx queue interrupts can be mapped in vector 1. And as current > > igb_uio only support only one vector, ixgbe VF PMD should use vector 0 > > for igb_uio and vector 1 for VFIO-PCI. Without this patch, VF Rx queue > > interrupt is mapped to vector 0 in register settings and mapped to > > VFIO vector 1 in vfio_enable_msix( ), and then all Rx queue interrupts = will > be missed. > > > > Fixes: b13bfab4cdbe ("eal: reserve VFIO vector zero for misc > > interrupt") > > Cc: stable@dpdk.org > > > > Signed-off-by: Wei Dai Tested-by: Jianwei Ma > > --- > > drivers/net/ixgbe/ixgbe_ethdev.c | 25 ++++++++++++++++++++++--- > > 1 file changed, 22 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c > > b/drivers/net/ixgbe/ixgbe_ethdev.c > > index 9ca5cbc..39a3d8c 100644 > > --- a/drivers/net/ixgbe/ixgbe_ethdev.c > > +++ b/drivers/net/ixgbe/ixgbe_ethdev.c > > @@ -5029,7 +5029,10 @@ ixgbevf_dev_start(struct rte_eth_dev *dev) > > > > /* check and configure queue intr-vector mapping */ > > if (dev->data->dev_conf.intr_conf.rxq !=3D 0) { > > - intr_vector =3D dev->data->nb_rx_queues; > > + /* According to datasheet, only vector 0/1/2 can be used, > > + * now only one vector is used for Rx queue > > + */ > > + intr_vector =3D 1; > > if (rte_intr_efd_enable(intr_handle, intr_vector)) > > return -1; > > } > > @@ -5556,9 +5559,12 @@ ixgbevf_dev_rx_queue_intr_enable(struct > > rte_eth_dev *dev, uint16_t queue_id) > > uint32_t mask; > > struct ixgbe_hw *hw =3D > > IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); > > + uint32_t vec =3D IXGBE_MISC_VEC_ID; > > > > mask =3D IXGBE_READ_REG(hw, IXGBE_VTEIMS); > > - mask |=3D (1 << IXGBE_MISC_VEC_ID); > > + if (rte_intr_allow_others(intr_handle)) > > + vec =3D IXGBE_RX_VEC_START; > > + mask |=3D (1 << vec); > > RTE_SET_USED(queue_id); > > IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask); > > > > @@ -5573,9 +5579,14 @@ ixgbevf_dev_rx_queue_intr_disable(struct > > rte_eth_dev *dev, uint16_t queue_id) > > uint32_t mask; > > struct ixgbe_hw *hw =3D > > IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); > > + struct rte_pci_device *pci_dev =3D RTE_ETH_DEV_TO_PCI(dev); > > + struct rte_intr_handle *intr_handle =3D &pci_dev->intr_handle; > > + uint32_t vec =3D IXGBE_MISC_VEC_ID; > > > > mask =3D IXGBE_READ_REG(hw, IXGBE_VTEIMS); > > - mask &=3D ~(1 << IXGBE_MISC_VEC_ID); > > + if (rte_intr_allow_others(intr_handle)) > > + vec =3D IXGBE_RX_VEC_START; > > + mask &=3D ~(1 << vec); > > RTE_SET_USED(queue_id); > > IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask); > > > > @@ -5717,6 +5728,7 @@ ixgbevf_configure_msix(struct rte_eth_dev > *dev) > > IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); > > uint32_t q_idx; > > uint32_t vector_idx =3D IXGBE_MISC_VEC_ID; > > + uint32_t base =3D IXGBE_MISC_VEC_ID; > > > > /* Configure VF other cause ivar */ > > ixgbevf_set_ivar_map(hw, -1, 1, vector_idx); @@ -5727,6 +5739,11 > @@ > > ixgbevf_configure_msix(struct rte_eth_dev *dev) > > if (!rte_intr_dp_is_en(intr_handle)) > > return; > > > > + if (rte_intr_allow_others(intr_handle)) { > > + base =3D IXGBE_RX_VEC_START; > > + vector_idx =3D IXGBE_RX_VEC_START; > > + } > > + > > /* Configure all RX queues of VF */ > > for (q_idx =3D 0; q_idx < dev->data->nb_rx_queues; q_idx++) { > > /* Force all queue use vector 0, > > @@ -5734,6 +5751,8 @@ ixgbevf_configure_msix(struct rte_eth_dev > *dev) > > */ > > ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx); > > intr_handle->intr_vec[q_idx] =3D vector_idx; > > + if (vector_idx < base + intr_handle->nb_efd - 1) > > + vector_idx++; > > } > > } > > > > -- > > 2.7.5