From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id A53C5A0487 for ; Fri, 5 Jul 2019 18:56:07 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D0D0D1BDF6; Fri, 5 Jul 2019 18:56:06 +0200 (CEST) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id 882C51BDF5 for ; Fri, 5 Jul 2019 18:56:04 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Jul 2019 09:56:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,455,1557212400"; d="scan'208";a="172717770" Received: from vmedvedk-mobl.ger.corp.intel.com (HELO [10.237.220.98]) ([10.237.220.98]) by FMSMGA003.fm.intel.com with ESMTP; 05 Jul 2019 09:56:02 -0700 To: Alex Kiselev , Honnappa Nagarahalli Cc: "Ruifeng Wang (Arm Technology China)" , "bruce.richardson@intel.com" , "dev@dpdk.org" , "Gavin Hu (Arm Technology China)" , nd References: <20190627093751.7746-1-ruifeng.wang@arm.com> <20190627093751.7746-3-ruifeng.wang@arm.com> <6daf7a76-1def-21df-d202-10b2a8f8582a@intel.com> From: "Medvedkin, Vladimir" Message-ID: <4b3964d2-29a3-2c44-885f-287e9e35434c@intel.com> Date: Fri, 5 Jul 2019 17:56:01 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.7.2 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US Subject: Re: [dpdk-dev] [PATCH v3 3/3] lib/lpm: memory orderings to avoid race conditions for v20 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Alex, On 05/07/2019 14:45, Alex Kiselev wrote: > Hi, > >> >> >>> As a general remark consider writing all of the tbl entries including >>> tbl8 with atomic_store. Now "lpm->tbl8[j] = new_tbl8_entry;" is looks like >>> >>> 1e9: 44 88 9c 47 40 01 00 mov >>> %r11b,0x2000140(%rdi,%rax,2) <-write first byte >>> 1f0: 02 >>> 1f1: 48 83 c0 01 add $0x1,%rax >>> 1f5: 42 88 8c 47 41 01 00 mov %cl,0x2000141(%rdi,%r8,2) <-write >>> second byte >>> 1fc: 02 >>> >>> This may cause an incorrect nexthop to be returned. If the byte with valid flag >>> is updated first, the old(and maybe invalid) next hop could be returned. >> +1 >> >> It is surprising that the compiler is not generating a single 32b store. As you mentioned 'relaxed' __atomic_store_n should be good. > Am I right that x86 platform is not affected by the bug since > store-store could not be reordered on x86? You right, x86 shouldn't be affected. If I understand asm correctly nexthop is written first for both _v20 and _v1604. Memory stores are retired in order. -- Regards, Vladimir