From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9072A45501; Wed, 26 Jun 2024 14:04:29 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5FA1C433E2; Wed, 26 Jun 2024 13:56:48 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by mails.dpdk.org (Postfix) with ESMTP id E88BC42E95 for ; Wed, 26 Jun 2024 13:45:15 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719402316; x=1750938316; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qSsqAmsHvOWXpLndscsU8AqLpPghGkGGvb2Br9BLY94=; b=flg5eFnZQH4b6QyV4k5bPXFL0bFEqqN96/qg+nk8j4llsfj3CXngOHNu lcN3LnBirxrtzot9VE8EVQPC41gdG6xQKlXWDACsFx3SGQCLq0d4vqhM1 SjZ1XoAud45RqIzo/gcBkivALK85P/t0V/IOeYkBNIMgxod6imvbww8Zg 4tD0Yyy/Hw18Ex61dplYU5+GdL5Sx5QHMS8plZkWWG5bPjgoQSTFfNekO dPNQWiuJyxgHwEP6haC6D9p9LMawkmVEJN5+lxOALIwuw88nLIYYQ6oaP qAj11TG9USVvBq+POaUU5q1u6L7Z/uLgSUUV6yqr7dollDzGWDoj05sGb Q==; X-CSE-ConnectionGUID: eoSYxHpERaO5q+2s/31Tgw== X-CSE-MsgGUID: b0KT3ch+SFONhjon6raD1A== X-IronPort-AV: E=McAfee;i="6700,10204,11114"; a="38979533" X-IronPort-AV: E=Sophos;i="6.08,266,1712646000"; d="scan'208";a="38979533" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jun 2024 04:45:15 -0700 X-CSE-ConnectionGUID: hip1UuKkTJKi7XCgSBgvOQ== X-CSE-MsgGUID: esMLnQDES7a2PLgT7P8rSA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,266,1712646000"; d="scan'208";a="43874254" Received: from unknown (HELO silpixa00401119.ir.intel.com) ([10.55.129.167]) by orviesa010.jf.intel.com with ESMTP; 26 Jun 2024 04:45:14 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Paul Greenwalt , ian.stokes@intel.com, bruce.richardson@intel.com Subject: [PATCH v4 079/103] net/ice/base: add E830 PTP init Date: Wed, 26 Jun 2024 12:42:07 +0100 Message-ID: <50587e8a86c300cb837189b4b67e010f5fc5c8a3.1719401848.git.anatoly.burakov@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Paul Greenwalt Add E830 PTP initialization flow. TXPP requires SW and HW timer clock synchronization which is done during the PTP initialization flow. The E810 and E830 PTP initialization flows are similar. The primary difference that E810 initializes the PHY via AQCs, and E830 does not initialize the external PHY. Signed-off-by: Paul Greenwalt Signed-off-by: Anatoly Burakov --- drivers/net/ice/base/ice_ptp_hw.c | 42 ++++++++++++++++++++++++++++--- 1 file changed, 39 insertions(+), 3 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 0d2968c528..1a25cf5434 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -911,6 +911,18 @@ static void ice_ptp_exec_tmr_cmd(struct ice_hw *hw) ice_flush(hw); } +/** + * ice_ptp_zero_syn_dlay - Set synchronization delay to zero + * @hw: pointer to HW struct + * + * Zero E810 and E830 specific PTP hardware clock synchronization delay. + */ +static void ice_ptp_zero_syn_dlay(struct ice_hw *hw) +{ + wr32(hw, GLTSYN_SYNC_DLAY, 0); + ice_flush(hw); +} + enum eth56g_res_type { ETH56G_PHY_REG, ETH56G_PHY_MEM, @@ -2368,9 +2380,10 @@ void ice_ptp_init_phy_model(struct ice_hw *hw) if (ice_is_e810(hw)) hw->phy_model = ICE_PHY_E810; + else if (ice_is_e830(hw)) + hw->phy_model = ICE_PHY_E830; else hw->phy_model = ICE_PHY_E822; - hw->phy_ports = ICE_NUM_EXTERNAL_PORTS; hw->max_phy_port = ICE_NUM_EXTERNAL_PORTS; } @@ -4934,8 +4947,7 @@ int ice_ptp_init_phy_e810(struct ice_hw *hw) */ static int ice_ptp_init_phc_e810(struct ice_hw *hw) { - /* Ensure synchronization delay is zero */ - wr32(hw, GLTSYN_SYNC_DLAY, 0); + ice_ptp_zero_syn_dlay(hw); /* Initialize the PHY */ return ice_ptp_init_phy_e810(hw); @@ -5451,6 +5463,24 @@ int ice_ptp_read_sdp_section_from_nvm(struct ice_hw *hw, bool *section_exist, return err; } +/* E830 functions + * + * The following functions operate on the E830 series devices. + * + */ + +/** + * ice_ptp_init_phc_e830 - Perform E830 specific PHC initialization + * @hw: pointer to HW struct + * + * Perform E830-specific PTP hardware clock initialization steps. + */ +static int ice_ptp_init_phc_e830(struct ice_hw *hw) +{ + ice_ptp_zero_syn_dlay(hw); + return 0; +} + /** * ice_ptp_write_direct_incval_e830 - Prep PHY port increment value change * @hw: pointer to HW struct @@ -6101,6 +6131,7 @@ void ice_ptp_reset_ts_memory(struct ice_hw *hw) ice_ptp_reset_ts_memory_e822(hw); break; case ICE_PHY_E810: + case ICE_PHY_E830: default: return; } @@ -6129,6 +6160,8 @@ int ice_ptp_init_phc(struct ice_hw *hw) return ice_ptp_init_phc_e810(hw); case ICE_PHY_E822: return ice_ptp_init_phc_e822(hw); + case ICE_PHY_E830: + return ice_ptp_init_phc_e830(hw); default: return ICE_ERR_NOT_SUPPORTED; } @@ -6151,6 +6184,9 @@ int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready) case ICE_PHY_ETH56G: return ice_get_phy_tx_tstamp_ready_eth56g(hw, block, tstamp_ready); + case ICE_PHY_E830: + return ice_get_phy_tx_tstamp_ready_e830(hw, block, + tstamp_ready); case ICE_PHY_E810: return ice_get_phy_tx_tstamp_ready_e810(hw, block, tstamp_ready); -- 2.43.0