From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9FD49A034C; Tue, 10 May 2022 04:57:23 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3F2EA410EE; Tue, 10 May 2022 04:57:23 +0200 (CEST) Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by mails.dpdk.org (Postfix) with ESMTP id 856D740DDA for ; Tue, 10 May 2022 04:57:21 +0200 (CEST) Received: from dggpeml500024.china.huawei.com (unknown [172.30.72.53]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4Ky2kL0QFbzhZ42; Tue, 10 May 2022 10:56:42 +0800 (CST) Received: from [127.0.0.1] (10.67.100.224) by dggpeml500024.china.huawei.com (7.185.36.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Tue, 10 May 2022 10:57:19 +0800 Subject: Re: [PATCH v4 1/2] config/arm: add SVE ACLE control flag To: Rahul Bhansali , , Ruifeng Wang , Jan Viktorin , Bruce Richardson CC: References: <20220505142744.1423344-1-rbhansali@marvell.com> <20220509101932.2403562-1-rbhansali@marvell.com> From: fengchengwen Message-ID: <51575bb0-1a36-721b-8f5c-83faf17c9612@huawei.com> Date: Tue, 10 May 2022 10:57:18 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 MIME-Version: 1.0 In-Reply-To: <20220509101932.2403562-1-rbhansali@marvell.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.67.100.224] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To dggpeml500024.china.huawei.com (7.185.36.10) X-CFilter-Loop: Reflected X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Reviewed-by: Chengwen Feng On 2022/5/9 18:19, Rahul Bhansali wrote: > This add the control flag for SVE ACLE to enable or disable > RTE_HAS_SVE_ACLE macro in the build. > > Signed-off-by: Rahul Bhansali > --- > Changes in v4: > - Resend patches. With v3, patches were not sent properly > in single series. > > Changes in v3: > - Moved sve_acle condition to be consider for > RTE_HAS_SVE_ACLE flag only. > > Changes in v2: > - Renamed the flag to sve_acle from sve > - Added double-indent. > > config/arm/meson.build | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/config/arm/meson.build b/config/arm/meson.build > index 8aead74086..6f8961eac8 100644 > --- a/config/arm/meson.build > +++ b/config/arm/meson.build > @@ -605,7 +605,7 @@ endif > > if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' > compile_time_cpuflags += ['RTE_CPUFLAG_SVE'] > - if (cc.check_header('arm_sve.h')) > + if (cc.check_header('arm_sve.h') and soc_config.get('sve_acle', true)) > dpdk_conf.set('RTE_HAS_SVE_ACLE', 1) > endif > endif > -- > 2.25.1 > > > . >