From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id EC7348D35 for ; Mon, 1 Feb 2016 09:05:18 +0100 (CET) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP; 01 Feb 2016 00:05:17 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,379,1449561600"; d="scan'208";a="905657766" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by fmsmga002.fm.intel.com with ESMTP; 01 Feb 2016 00:05:18 -0800 Received: from fmsmsx152.amr.corp.intel.com (10.18.125.5) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.248.2; Mon, 1 Feb 2016 00:05:17 -0800 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by FMSMSX152.amr.corp.intel.com (10.18.125.5) with Microsoft SMTP Server (TLS) id 14.3.248.2; Mon, 1 Feb 2016 00:05:17 -0800 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.215]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.231]) with mapi id 14.03.0248.002; Mon, 1 Feb 2016 16:05:15 +0800 From: "Qiu, Michael" To: "Lu, Wenzhuo" , "dev@dpdk.org" Thread-Topic: [PATCH v2] ixgbe: Fix disable interrupt twice Thread-Index: AQHRWlokuxzst+DuYUqlXTIjOup9yQ== Date: Mon, 1 Feb 2016 08:05:15 +0000 Message-ID: <533710CFB86FA344BFBF2D6802E6028622F28091@SHSMSX101.ccr.corp.intel.com> References: <1454046700-20843-1-git-send-email-michael.qiu@intel.com> <1454047090-21274-1-git-send-email-michael.qiu@intel.com> <6A0DE07E22DDAD4C9103DF62FEBC0909034256DA@shsmsx102.ccr.corp.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="Windows-1252" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2] ixgbe: Fix disable interrupt twice X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 01 Feb 2016 08:05:19 -0000 On 1/29/2016 4:07 PM, Lu, Wenzhuo wrote:=0A= > Hi Michael,=0A= >=0A= >> -----Original Message-----=0A= >> From: Qiu, Michael=0A= >> Sent: Friday, January 29, 2016 1:58 PM=0A= >> To: dev@dpdk.org=0A= >> Cc: Zhou, Danny; Liu, Yong; Liang, Cunming; Lu, Wenzhuo; Qiu, Michael=0A= >> Subject: [PATCH v2] ixgbe: Fix disable interrupt twice=0A= >>=0A= >> Currently, ixgbe vf and pf will disable interrupt twice in stop stage an= d uninit=0A= >> stage. It will cause an error:=0A= >>=0A= >> testpmd> quit=0A= >>=0A= >> Shutting down port 0...=0A= >> Stopping ports...=0A= >> Done=0A= >> Closing ports...=0A= >> EAL: Error disabling MSI-X interrupts for fd 26=0A= >> Done=0A= >>=0A= >> Becasue the interrupt already been disabled in stop stage.=0A= >> Since it is enabled in init stage, better remove from stop stage.=0A= > I'm afraid it=92s not a good idea to just remove the intr_disable from de= v_stop.=0A= > I think dev_stop have the chance to be used independently with dev_unint.= In this scenario, we still need intr_disable, right?=0A= > Maybe what we need is some check before we disable the intr:)=0A= =0A= Yes, indeed we need some check in disable intr, but it need additional=0A= fields in "struct rte_intr_handle", and it's much saft to do so, but as=0A= I check i40e/fm10k code, only ixgbe disable it in dev_stop().=0A= =0A= On other hand, if we remove it in dev_stop, any side effect? In ixgbe=0A= start, it will always disable it first and then re-enable it, so it's safe.= =0A= =0A= Thanks,=0A= Michael=0A= >=0A= =0A=