From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id E91D97FF9 for ; Mon, 24 Nov 2014 09:00:18 +0100 (CET) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP; 24 Nov 2014 00:11:04 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.07,447,1413270000"; d="scan'208";a="612967063" Received: from pgsmsx107.gar.corp.intel.com ([10.221.44.105]) by orsmga001.jf.intel.com with ESMTP; 24 Nov 2014 00:11:03 -0800 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by PGSMSX107.gar.corp.intel.com (10.221.44.105) with Microsoft SMTP Server (TLS) id 14.3.195.1; Mon, 24 Nov 2014 16:11:02 +0800 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.110]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.86]) with mapi id 14.03.0195.001; Mon, 24 Nov 2014 16:11:01 +0800 From: "Qiu, Michael" To: Chao Zhu , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH v3 03/14] Add byte order operations for IBM Power architecture Thread-Index: AQHQByCV4JlOoLoj906SXF/i6u1wAA== Date: Mon, 24 Nov 2014 08:11:01 +0000 Message-ID: <533710CFB86FA344BFBF2D6802E60286C99F43@SHSMSX101.ccr.corp.intel.com> References: <1416792142-23132-1-git-send-email-chaozhu@linux.vnet.ibm.com> <1416792142-23132-4-git-send-email-chaozhu@linux.vnet.ibm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v3 03/14] Add byte order operations for IBM Power architecture X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 24 Nov 2014 08:00:20 -0000 On 11/23/2014 9:22 PM, Chao Zhu wrote:=0A= > This patch adds architecture specific byte order operations for IBM Power= =0A= > architecture. Power architecture support both big endian and little=0A= > endian. This patch also adds a RTE_ARCH_BIG_ENDIAN micro.=0A= >=0A= > Signed-off-by: Chao Zhu =0A= > ---=0A= > config/defconfig_ppc_64-power8-linuxapp-gcc | 1 +=0A= > .../common/include/arch/ppc_64/rte_byteorder.h | 150 ++++++++++++++= ++++++=0A= > 2 files changed, 151 insertions(+), 0 deletions(-)=0A= > create mode 100644 lib/librte_eal/common/include/arch/ppc_64/rte_byteord= er.h=0A= >=0A= > diff --git a/config/defconfig_ppc_64-power8-linuxapp-gcc b/config/defconf= ig_ppc_64-power8-linuxapp-gcc=0A= > index 97d72ff..b10f60c 100644=0A= > --- a/config/defconfig_ppc_64-power8-linuxapp-gcc=0A= > +++ b/config/defconfig_ppc_64-power8-linuxapp-gcc=0A= > @@ -34,6 +34,7 @@ CONFIG_RTE_MACHINE=3D"power8"=0A= > =0A= > CONFIG_RTE_ARCH=3D"ppc_64"=0A= > CONFIG_RTE_ARCH_PPC_64=3Dy=0A= > +CONFIG_RTE_ARCH_BIG_ENDIAN=3Dy=0A= =0A= Does this means default is Big Endian, if I runs it in little endian=0A= mode, I need to change it manually?=0A= > =0A= > CONFIG_RTE_TOOLCHAIN=3D"gcc"=0A= > CONFIG_RTE_TOOLCHAIN_GCC=3Dy=0A= > diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_byteorder.h b/= lib/librte_eal/common/include/arch/ppc_64/rte_byteorder.h=0A= > new file mode 100644=0A= > index 0000000..a593e8a=0A= > --- /dev/null=0A= > +++ b/lib/librte_eal/common/include/arch/ppc_64/rte_byteorder.h=0A= > @@ -0,0 +1,150 @@=0A= > +/*=0A= > + * BSD LICENSE=0A= > + *=0A= > + * Copyright (C) IBM Corporation 2014.=0A= > + *=0A= > + * Redistribution and use in source and binary forms, with or without= =0A= > + * modification, are permitted provided that the following conditions= =0A= > + * are met:=0A= > + *=0A= > + * * Redistributions of source code must retain the above copyright= =0A= > + * notice, this list of conditions and the following disclaimer.= =0A= > + * * Redistributions in binary form must reproduce the above copyrig= ht=0A= > + * notice, this list of conditions and the following disclaimer in= =0A= > + * the documentation and/or other materials provided with the=0A= > + * distribution.=0A= > + * * Neither the name of IBM Corporation nor the names of its=0A= > + * contributors may be used to endorse or promote products derived= =0A= > + * from this software without specific prior written permission.= =0A= > + *=0A= > + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS= =0A= > + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT= =0A= > + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS F= OR=0A= > + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGH= T=0A= > + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTA= L,=0A= > + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT=0A= > + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF US= E,=0A= > + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON A= NY=0A= > + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT= =0A= > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE U= SE=0A= > + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE= .=0A= > +*/=0A= > +=0A= > +/* Inspired from FreeBSD src/sys/powerpc/include/endian.h=0A= > + * Copyright (c) 1987, 1991, 1993=0A= > + * The Regents of the University of California. All rights reserved.=0A= > +*/=0A= > +=0A= > +#ifndef _RTE_BYTEORDER_PPC_64_H_=0A= > +#define _RTE_BYTEORDER_PPC_64_H_=0A= > +=0A= > +#ifdef __cplusplus=0A= > +extern "C" {=0A= > +#endif=0A= > +=0A= > +#include "generic/rte_byteorder.h"=0A= > +=0A= > +/*=0A= > + * An architecture-optimized byte swap for a 16-bit value.=0A= > + *=0A= > + * Do not use this function directly. The preferred function is rte_bswa= p16().=0A= > + */=0A= > +static inline uint16_t rte_arch_bswap16(uint16_t _x)=0A= > +{=0A= > + return ((_x >> 8) | ((_x << 8) & 0xff00));=0A= > +}=0A= > +=0A= > +/*=0A= > + * An architecture-optimized byte swap for a 32-bit value.=0A= > + *=0A= > + * Do not use this function directly. The preferred function is rte_bswa= p32().=0A= > + */=0A= > +static inline uint32_t rte_arch_bswap32(uint32_t _x)=0A= > +{=0A= > + return ((_x >> 24) | ((_x >> 8) & 0xff00) | ((_x << 8) & 0xff0000) |=0A= > + ((_x << 24) & 0xff000000));=0A= > +}=0A= > +=0A= > +/*=0A= > + * An architecture-optimized byte swap for a 64-bit value.=0A= > + *=0A= > + * Do not use this function directly. The preferred function is rte_bsw= ap64().=0A= > + */=0A= > +/* 64-bit mode */=0A= > +static inline uint64_t rte_arch_bswap64(uint64_t _x)=0A= > +{=0A= > + return ((_x >> 56) | ((_x >> 40) & 0xff00) | ((_x >> 24) & 0xff0000) |= =0A= > + ((_x >> 8) & 0xff000000) | ((_x << 8) & (0xffULL << 32)) |=0A= > + ((_x << 24) & (0xffULL << 40)) |=0A= > + ((_x << 40) & (0xffULL << 48)) | ((_x << 56)));=0A= > +}=0A= > +=0A= > +#ifndef RTE_FORCE_INTRINSICS=0A= > +#define rte_bswap16(x) ((uint16_t)(__builtin_constant_p(x) ? \=0A= > + rte_constant_bswap16(x) : \=0A= > + rte_arch_bswap16(x)))=0A= > +=0A= > +#define rte_bswap32(x) ((uint32_t)(__builtin_constant_p(x) ? \=0A= > + rte_constant_bswap32(x) : \=0A= > + rte_arch_bswap32(x)))=0A= > +=0A= > +#define rte_bswap64(x) ((uint64_t)(__builtin_constant_p(x) ? \=0A= > + rte_constant_bswap64(x) : \=0A= > + rte_arch_bswap64(x)))=0A= > +#else=0A= > +/*=0A= > + * __builtin_bswap16 is only available gcc 4.8 and upwards=0A= > + */=0A= > +#if __GNUC__ < 4 || (__GNUC__ =3D=3D 4 && __GNUC_MINOR__ < 8)=0A= > +#define rte_bswap16(x) ((uint16_t)(__builtin_constant_p(x) ? \=0A= > + rte_constant_bswap16(x) : \=0A= > + rte_arch_bswap16(x)))=0A= > +#endif=0A= > +#endif=0A= > +=0A= > +/* Power 8 have both little endian and big endian mode =0A= > + * Power 7 only support big endian=0A= =0A= Are you sure about this ? What I've heard is that all power CPU(at least=0A= Power7 and 8) supports, but not check the spec.=0A= > + */=0A= > +#ifndef RTE_ARCH_BIG_ENDIAN=0A= > +=0A= > +#define rte_cpu_to_le_16(x) (x)=0A= > +#define rte_cpu_to_le_32(x) (x)=0A= > +#define rte_cpu_to_le_64(x) (x)=0A= > +=0A= > +#define rte_cpu_to_be_16(x) rte_bswap16(x)=0A= > +#define rte_cpu_to_be_32(x) rte_bswap32(x)=0A= > +#define rte_cpu_to_be_64(x) rte_bswap64(x)=0A= > +=0A= > +#define rte_le_to_cpu_16(x) (x)=0A= > +#define rte_le_to_cpu_32(x) (x)=0A= > +#define rte_le_to_cpu_64(x) (x)=0A= > +=0A= > +#define rte_be_to_cpu_16(x) rte_bswap16(x)=0A= > +#define rte_be_to_cpu_32(x) rte_bswap32(x)=0A= > +#define rte_be_to_cpu_64(x) rte_bswap64(x)=0A= > +=0A= > +#else=0A= > +=0A= > +#define rte_cpu_to_le_16(x) rte_bswap16(x)=0A= > +#define rte_cpu_to_le_32(x) rte_bswap32(x)=0A= > +#define rte_cpu_to_le_64(x) rte_bswap64(x)=0A= > +=0A= > +#define rte_cpu_to_be_16(x) (x)=0A= > +#define rte_cpu_to_be_32(x) (x)=0A= > +#define rte_cpu_to_be_64(x) (x)=0A= > +=0A= > +#define rte_le_to_cpu_16(x) rte_bswap16(x)=0A= > +#define rte_le_to_cpu_32(x) rte_bswap32(x)=0A= > +#define rte_le_to_cpu_64(x) rte_bswap64(x)=0A= > +=0A= > +#define rte_be_to_cpu_16(x) (x)=0A= > +#define rte_be_to_cpu_32(x) (x)=0A= > +#define rte_be_to_cpu_64(x) (x)=0A= > +#endif=0A= > +=0A= > +#ifdef __cplusplus=0A= > +}=0A= > +#endif=0A= > +=0A= > +#endif /* _RTE_BYTEORDER_PPC_64_H_ */=0A= > +=0A= =0A=