From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id B05A7DE0 for ; Thu, 4 Dec 2014 03:30:02 +0100 (CET) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga103.jf.intel.com with ESMTP; 03 Dec 2014 18:28:16 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.04,691,1406617200"; d="scan'208";a="493313258" Received: from kmsmsx152.gar.corp.intel.com ([172.21.73.87]) by orsmga003.jf.intel.com with ESMTP; 03 Dec 2014 18:26:34 -0800 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by KMSMSX152.gar.corp.intel.com (172.21.73.87) with Microsoft SMTP Server (TLS) id 14.3.195.1; Thu, 4 Dec 2014 10:28:08 +0800 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.110]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.86]) with mapi id 14.03.0195.001; Thu, 4 Dec 2014 10:28:07 +0800 From: "Qiu, Michael" To: Thomas Monjalon , "dev@dpdk.org" Thread-Topic: [PATCH 1/2] eal: detect endianness Thread-Index: AQHQDz/AjmPcs+k3nUirJ6Voc/wGwA== Date: Thu, 4 Dec 2014 02:28:06 +0000 Message-ID: <533710CFB86FA344BFBF2D6802E60286C9C86D@SHSMSX101.ccr.corp.intel.com> References: <283531301.lWbIahXLyM@xps13> <1417639668-23500-1-git-send-email-thomas.monjalon@6wind.com> <1417639668-23500-2-git-send-email-thomas.monjalon@6wind.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Cc: Chao Zhu Subject: Re: [dpdk-dev] [PATCH 1/2] eal: detect endianness X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 04 Dec 2014 02:30:03 -0000 On 12/4/2014 5:26 AM, Thomas Monjalon wrote:=0A= > There is no standard to check endianness.=0A= > So we need to try different checks.=0A= > Previous trials were done in testpmd (see commits=0A= > 51f694dd40f56 and 64741f237cf29) without full success.=0A= > This one is not guaranteed to work everywhere so it could=0A= > evolve when exceptions are found.=0A= >=0A= > If endianness is not detected, there is a fallback on x86=0A= > to little endian. It could be forced before doing detection=0A= > but it would add some arch-dependent code in the generic header.=0A= >=0A= > The option CONFIG_RTE_ARCH_BIG_ENDIAN introduced for IBM Power only=0A= > (commit a982ec81d84d53) can be removed. A compile-time check is better.= =0A= >=0A= > Signed-off-by: Thomas Monjalon =0A= > ---=0A= > config/defconfig_ppc_64-power8-linuxapp-gcc | 1 -=0A= > .../common/include/arch/ppc_64/rte_byteorder.h | 4 ++--=0A= > .../common/include/arch/x86/rte_byteorder.h | 4 ++++=0A= > .../common/include/generic/rte_byteorder.h | 28 ++++++++++++++++= ++++++=0A= > 4 files changed, 34 insertions(+), 3 deletions(-)=0A= >=0A= > diff --git a/config/defconfig_ppc_64-power8-linuxapp-gcc b/config/defconf= ig_ppc_64-power8-linuxapp-gcc=0A= > index 48018c3..d97a885 100644=0A= > --- a/config/defconfig_ppc_64-power8-linuxapp-gcc=0A= > +++ b/config/defconfig_ppc_64-power8-linuxapp-gcc=0A= > @@ -34,7 +34,6 @@ CONFIG_RTE_MACHINE=3D"power8"=0A= > =0A= > CONFIG_RTE_ARCH=3D"ppc_64"=0A= > CONFIG_RTE_ARCH_PPC_64=3Dy=0A= > -CONFIG_RTE_ARCH_BIG_ENDIAN=3Dy=0A= > CONFIG_RTE_ARCH_64=3Dy=0A= > =0A= > CONFIG_RTE_TOOLCHAIN=3D"gcc"=0A= > diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_byteorder.h b/= lib/librte_eal/common/include/arch/ppc_64/rte_byteorder.h=0A= > index 1a89051..80436f2 100644=0A= > --- a/lib/librte_eal/common/include/arch/ppc_64/rte_byteorder.h=0A= > +++ b/lib/librte_eal/common/include/arch/ppc_64/rte_byteorder.h=0A= > @@ -105,7 +105,7 @@ static inline uint64_t rte_arch_bswap64(uint64_t _x)= =0A= > /* Power 8 have both little endian and big endian mode=0A= > * Power 7 only support big endian=0A= > */=0A= > -#ifndef RTE_ARCH_BIG_ENDIAN=0A= > +#if RTE_BYTE_ORDER =3D=3D RTE_LITTLE_ENDIAN=0A= > =0A= > #define rte_cpu_to_le_16(x) (x)=0A= > #define rte_cpu_to_le_32(x) (x)=0A= > @@ -123,7 +123,7 @@ static inline uint64_t rte_arch_bswap64(uint64_t _x)= =0A= > #define rte_be_to_cpu_32(x) rte_bswap32(x)=0A= > #define rte_be_to_cpu_64(x) rte_bswap64(x)=0A= > =0A= > -#else=0A= > +#else /* RTE_BIG_ENDIAN */=0A= > =0A= > #define rte_cpu_to_le_16(x) rte_bswap16(x)=0A= > #define rte_cpu_to_le_32(x) rte_bswap32(x)=0A= > diff --git a/lib/librte_eal/common/include/arch/x86/rte_byteorder.h b/lib= /librte_eal/common/include/arch/x86/rte_byteorder.h=0A= > index 1aa6985..ffdb6ef 100644=0A= > --- a/lib/librte_eal/common/include/arch/x86/rte_byteorder.h=0A= > +++ b/lib/librte_eal/common/include/arch/x86/rte_byteorder.h=0A= > @@ -40,6 +40,10 @@ extern "C" {=0A= > =0A= > #include "generic/rte_byteorder.h"=0A= > =0A= > +#ifndef RTE_BYTE_ORDER=0A= > +#define RTE_BYTE_ORDER RTE_LITTLE_ENDIAN=0A= > +#endif=0A= > +=0A= > /*=0A= > * An architecture-optimized byte swap for a 16-bit value.=0A= > *=0A= > diff --git a/lib/librte_eal/common/include/generic/rte_byteorder.h b/lib/= librte_eal/common/include/generic/rte_byteorder.h=0A= > index 9358136..ea23fdf 100644=0A= > --- a/lib/librte_eal/common/include/generic/rte_byteorder.h=0A= > +++ b/lib/librte_eal/common/include/generic/rte_byteorder.h=0A= > @@ -44,6 +44,34 @@=0A= > */=0A= > =0A= > #include =0A= > +#ifdef RTE_EXEC_ENV_BSDAPP=0A= > +#include =0A= > +#else=0A= > +#include =0A= > +#endif=0A= > +=0A= > +/*=0A= > + * Compile-time endianness detection=0A= > + */=0A= > +#define RTE_BIG_ENDIAN 1=0A= > +#define RTE_LITTLE_ENDIAN 2=0A= > +#if defined __BYTE_ORDER=0A= > +#if __BYTE_ORDER =3D=3D __BIG_ENDIAN=0A= > +#define RTE_BYTE_ORDER RTE_BIG_ENDIAN=0A= > +#elif __BYTE_ORDER =3D=3D __LITTLE_ENDIAN=0A= > +#define RTE_BYTE_ORDER RTE_LITTLE_ENDIAN=0A= > +#endif /* __BYTE_ORDER */=0A= > +#elif defined __BYTE_ORDER__=0A= > +#if __BYTE_ORDER__ =3D=3D __ORDER_BIG_ENDIAN__=0A= > +#define RTE_BYTE_ORDER RTE_BIG_ENDIAN=0A= > +#elif __BYTE_ORDER__ =3D=3D __ORDER_LITTLE_ENDIAN__=0A= > +#define RTE_BYTE_ORDER RTE_LITTLE_ENDIAN=0A= > +#endif /* __BYTE_ORDER__ */=0A= > +#elif defined __BIG_ENDIAN__=0A= > +#define RTE_BYTE_ORDER RTE_BIG_ENDIAN=0A= > +#elif defined __LITTLE_ENDIAN__=0A= > +#define RTE_BYTE_ORDER RTE_LITTLE_ENDIAN=0A= > +#endif=0A= =0A= What do you think about :=0A= =0A= +/*=0A= + * Compile-time endianness detection=0A= + */=0A= +#define RTE_BIG_ENDIAN 1=0A= +#define RTE_LITTLE_ENDIAN 2=0A= +if defined __BYTE_ORDER__ /* Prefer gcc build-in macros */=0A= +#if __BYTE_ORDER__ =3D=3D __ORDER_BIG_ENDIAN__=0A= +#define RTE_BYTE_ORDER RTE_BIG_ENDIAN=0A= +#elif __BYTE_ORDER__ =3D=3D __ORDER_LITTLE_ENDIAN__=0A= +#define RTE_BYTE_ORDER RTE_LITTLE_ENDIAN=0A= +#endif /* __BYTE_ORDER__ */=0A= +#else=0A= +#if defined RTE_EXEC_ENV_BSDAPP=0A= +#include =0A= +#else=0A= +#include =0A= +#endif=0A= +#if defined __BYTE_ORDER=0A= +#if __BYTE_ORDER =3D=3D __BIG_ENDIAN=0A= +#define RTE_BYTE_ORDER RTE_BIG_ENDIAN=0A= +#elif __BYTE_ORDER =3D=3D __LITTLE_ENDIAN=0A= +#define RTE_BYTE_ORDER RTE_LITTLE_ENDIAN=0A= +#endif /* __BYTE_ORDER */=0A= +#elif defined __BIG_ENDIAN__=0A= +#define RTE_BYTE_ORDER RTE_BIG_ENDIAN=0A= +#elif defined __LITTLE_ENDIAN__=0A= +#define RTE_BYTE_ORDER RTE_LITTLE_ENDIAN=0A= +#endif=0A= +#endif=0A= > =0A= > /*=0A= > * An internal function to swap bytes in a 16-bit value.=0A= =0A=