From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 4B72A5A76 for ; Thu, 5 Mar 2015 14:23:47 +0100 (CET) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP; 05 Mar 2015 05:22:17 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,347,1422950400"; d="scan'208";a="687338785" Received: from pgsmsx102.gar.corp.intel.com ([10.221.44.80]) by fmsmga002.fm.intel.com with ESMTP; 05 Mar 2015 05:23:45 -0800 Received: from shsmsx104.ccr.corp.intel.com (10.239.110.15) by PGSMSX102.gar.corp.intel.com (10.221.44.80) with Microsoft SMTP Server (TLS) id 14.3.195.1; Thu, 5 Mar 2015 21:23:44 +0800 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.192]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.161]) with mapi id 14.03.0195.001; Thu, 5 Mar 2015 21:23:43 +0800 From: "Qiu, Michael" To: "dev@dpdk.org" Thread-Topic: =?Windows-1252?Q?[PATCH_3/3]_librte=5Feal/common:_Fix_redeclaration_of_en?= =?Windows-1252?Q?umerator_=91REG=5FEAX=92?= Thread-Index: AQHQV0aJJJU31JH3L0amHBzVEfuprw== Date: Thu, 5 Mar 2015 13:23:42 +0000 Message-ID: <533710CFB86FA344BFBF2D6802E60286CEEEA7@SHSMSX101.ccr.corp.intel.com> References: <1425561339-13300-1-git-send-email-michael.qiu@intel.com> <1425561339-13300-4-git-send-email-michael.qiu@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="Windows-1252" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] =?windows-1252?q?=5BPATCH_3/3=5D_librte=5Feal/common?= =?windows-1252?q?=3A_Fix_redeclaration_of_enumerator_=91REG=5FEAX=92?= X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Mar 2015 13:23:49 -0000 On 3/5/2015 9:16 PM, Qiu, Michael wrote:=0A= > include/rte_cpuflags.h:154:2: error: redeclaration of enumerator =91REG_E= AX=92=0A= > In file included from /usr/include/signal.h:358:0,=0A= > from /usr/include/sys/wait.h:30,=0A= > from /root/dpdk/app/test/test_mp_secondary.c:50:=0A= > /usr/include/sys/ucontext.h:180:3: note: previous definition of =91REG_EA= X=92 was here=0A= >=0A= > In i686, from REG_EAX to REG_EDX are all defined in=0A= > /usr/include/sys/ucontext.h=0A= >=0A= > Rename to CPU_REG_EAX to avoid this issue.=0A= >=0A= > Signed-off-by: Michael Qou =0A= =0A= Sorry, Michael Qou--> Michael Qiu=0A= =0A= Thanks,=0A= Michael=0A= > ---=0A= > .../common/include/arch/x86/rte_cpuflags.h | 210 ++++++++++-----= ------=0A= > 1 file changed, 105 insertions(+), 105 deletions(-)=0A= >=0A= > diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h b/lib/= librte_eal/common/include/arch/x86/rte_cpuflags.h=0A= > index a58dd7b..f367b91 100644=0A= > --- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h=0A= > +++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h=0A= > @@ -151,104 +151,104 @@ enum rte_cpu_flag_t {=0A= > };=0A= > =0A= > enum cpu_register_t {=0A= > - REG_EAX =3D 0,=0A= > - REG_EBX,=0A= > - REG_ECX,=0A= > - REG_EDX,=0A= > + CPU_REG_EAX =3D 0,=0A= > + CPU_REG_EBX,=0A= > + CPU_REG_ECX,=0A= > + CPU_REG_EDX,=0A= > };=0A= > =0A= > static const struct feature_entry cpu_feature_table[] =3D {=0A= > - FEAT_DEF(SSE3, 0x00000001, 0, REG_ECX, 0)=0A= > - FEAT_DEF(PCLMULQDQ, 0x00000001, 0, REG_ECX, 1)=0A= > - FEAT_DEF(DTES64, 0x00000001, 0, REG_ECX, 2)=0A= > - FEAT_DEF(MONITOR, 0x00000001, 0, REG_ECX, 3)=0A= > - FEAT_DEF(DS_CPL, 0x00000001, 0, REG_ECX, 4)=0A= > - FEAT_DEF(VMX, 0x00000001, 0, REG_ECX, 5)=0A= > - FEAT_DEF(SMX, 0x00000001, 0, REG_ECX, 6)=0A= > - FEAT_DEF(EIST, 0x00000001, 0, REG_ECX, 7)=0A= > - FEAT_DEF(TM2, 0x00000001, 0, REG_ECX, 8)=0A= > - FEAT_DEF(SSSE3, 0x00000001, 0, REG_ECX, 9)=0A= > - FEAT_DEF(CNXT_ID, 0x00000001, 0, REG_ECX, 10)=0A= > - FEAT_DEF(FMA, 0x00000001, 0, REG_ECX, 12)=0A= > - FEAT_DEF(CMPXCHG16B, 0x00000001, 0, REG_ECX, 13)=0A= > - FEAT_DEF(XTPR, 0x00000001, 0, REG_ECX, 14)=0A= > - FEAT_DEF(PDCM, 0x00000001, 0, REG_ECX, 15)=0A= > - FEAT_DEF(PCID, 0x00000001, 0, REG_ECX, 17)=0A= > - FEAT_DEF(DCA, 0x00000001, 0, REG_ECX, 18)=0A= > - FEAT_DEF(SSE4_1, 0x00000001, 0, REG_ECX, 19)=0A= > - FEAT_DEF(SSE4_2, 0x00000001, 0, REG_ECX, 20)=0A= > - FEAT_DEF(X2APIC, 0x00000001, 0, REG_ECX, 21)=0A= > - FEAT_DEF(MOVBE, 0x00000001, 0, REG_ECX, 22)=0A= > - FEAT_DEF(POPCNT, 0x00000001, 0, REG_ECX, 23)=0A= > - FEAT_DEF(TSC_DEADLINE, 0x00000001, 0, REG_ECX, 24)=0A= > - FEAT_DEF(AES, 0x00000001, 0, REG_ECX, 25)=0A= > - FEAT_DEF(XSAVE, 0x00000001, 0, REG_ECX, 26)=0A= > - FEAT_DEF(OSXSAVE, 0x00000001, 0, REG_ECX, 27)=0A= > - FEAT_DEF(AVX, 0x00000001, 0, REG_ECX, 28)=0A= > - FEAT_DEF(F16C, 0x00000001, 0, REG_ECX, 29)=0A= > - FEAT_DEF(RDRAND, 0x00000001, 0, REG_ECX, 30)=0A= > -=0A= > - FEAT_DEF(FPU, 0x00000001, 0, REG_EDX, 0)=0A= > - FEAT_DEF(VME, 0x00000001, 0, REG_EDX, 1)=0A= > - FEAT_DEF(DE, 0x00000001, 0, REG_EDX, 2)=0A= > - FEAT_DEF(PSE, 0x00000001, 0, REG_EDX, 3)=0A= > - FEAT_DEF(TSC, 0x00000001, 0, REG_EDX, 4)=0A= > - FEAT_DEF(MSR, 0x00000001, 0, REG_EDX, 5)=0A= > - FEAT_DEF(PAE, 0x00000001, 0, REG_EDX, 6)=0A= > - FEAT_DEF(MCE, 0x00000001, 0, REG_EDX, 7)=0A= > - FEAT_DEF(CX8, 0x00000001, 0, REG_EDX, 8)=0A= > - FEAT_DEF(APIC, 0x00000001, 0, REG_EDX, 9)=0A= > - FEAT_DEF(SEP, 0x00000001, 0, REG_EDX, 11)=0A= > - FEAT_DEF(MTRR, 0x00000001, 0, REG_EDX, 12)=0A= > - FEAT_DEF(PGE, 0x00000001, 0, REG_EDX, 13)=0A= > - FEAT_DEF(MCA, 0x00000001, 0, REG_EDX, 14)=0A= > - FEAT_DEF(CMOV, 0x00000001, 0, REG_EDX, 15)=0A= > - FEAT_DEF(PAT, 0x00000001, 0, REG_EDX, 16)=0A= > - FEAT_DEF(PSE36, 0x00000001, 0, REG_EDX, 17)=0A= > - FEAT_DEF(PSN, 0x00000001, 0, REG_EDX, 18)=0A= > - FEAT_DEF(CLFSH, 0x00000001, 0, REG_EDX, 19)=0A= > - FEAT_DEF(DS, 0x00000001, 0, REG_EDX, 21)=0A= > - FEAT_DEF(ACPI, 0x00000001, 0, REG_EDX, 22)=0A= > - FEAT_DEF(MMX, 0x00000001, 0, REG_EDX, 23)=0A= > - FEAT_DEF(FXSR, 0x00000001, 0, REG_EDX, 24)=0A= > - FEAT_DEF(SSE, 0x00000001, 0, REG_EDX, 25)=0A= > - FEAT_DEF(SSE2, 0x00000001, 0, REG_EDX, 26)=0A= > - FEAT_DEF(SS, 0x00000001, 0, REG_EDX, 27)=0A= > - FEAT_DEF(HTT, 0x00000001, 0, REG_EDX, 28)=0A= > - FEAT_DEF(TM, 0x00000001, 0, REG_EDX, 29)=0A= > - FEAT_DEF(PBE, 0x00000001, 0, REG_EDX, 31)=0A= > -=0A= > - FEAT_DEF(DIGTEMP, 0x00000006, 0, REG_EAX, 0)=0A= > - FEAT_DEF(TRBOBST, 0x00000006, 0, REG_EAX, 1)=0A= > - FEAT_DEF(ARAT, 0x00000006, 0, REG_EAX, 2)=0A= > - FEAT_DEF(PLN, 0x00000006, 0, REG_EAX, 4)=0A= > - FEAT_DEF(ECMD, 0x00000006, 0, REG_EAX, 5)=0A= > - FEAT_DEF(PTM, 0x00000006, 0, REG_EAX, 6)=0A= > -=0A= > - FEAT_DEF(MPERF_APERF_MSR, 0x00000006, 0, REG_ECX, 0)=0A= > - FEAT_DEF(ACNT2, 0x00000006, 0, REG_ECX, 1)=0A= > - FEAT_DEF(ENERGY_EFF, 0x00000006, 0, REG_ECX, 3)=0A= > -=0A= > - FEAT_DEF(FSGSBASE, 0x00000007, 0, REG_EBX, 0)=0A= > - FEAT_DEF(BMI1, 0x00000007, 0, REG_EBX, 2)=0A= > - FEAT_DEF(HLE, 0x00000007, 0, REG_EBX, 4)=0A= > - FEAT_DEF(AVX2, 0x00000007, 0, REG_EBX, 5)=0A= > - FEAT_DEF(SMEP, 0x00000007, 0, REG_EBX, 6)=0A= > - FEAT_DEF(BMI2, 0x00000007, 0, REG_EBX, 7)=0A= > - FEAT_DEF(ERMS, 0x00000007, 0, REG_EBX, 8)=0A= > - FEAT_DEF(INVPCID, 0x00000007, 0, REG_EBX, 10)=0A= > - FEAT_DEF(RTM, 0x00000007, 0, REG_EBX, 11)=0A= > -=0A= > - FEAT_DEF(LAHF_SAHF, 0x80000001, 0, REG_ECX, 0)=0A= > - FEAT_DEF(LZCNT, 0x80000001, 0, REG_ECX, 4)=0A= > -=0A= > - FEAT_DEF(SYSCALL, 0x80000001, 0, REG_EDX, 11)=0A= > - FEAT_DEF(XD, 0x80000001, 0, REG_EDX, 20)=0A= > - FEAT_DEF(1GB_PG, 0x80000001, 0, REG_EDX, 26)=0A= > - FEAT_DEF(RDTSCP, 0x80000001, 0, REG_EDX, 27)=0A= > - FEAT_DEF(EM64T, 0x80000001, 0, REG_EDX, 29)=0A= > -=0A= > - FEAT_DEF(INVTSC, 0x80000007, 0, REG_EDX, 8)=0A= > + FEAT_DEF(SSE3, 0x00000001, 0, CPU_REG_ECX, 0)=0A= > + FEAT_DEF(PCLMULQDQ, 0x00000001, 0, CPU_REG_ECX, 1)=0A= > + FEAT_DEF(DTES64, 0x00000001, 0, CPU_REG_ECX, 2)=0A= > + FEAT_DEF(MONITOR, 0x00000001, 0, CPU_REG_ECX, 3)=0A= > + FEAT_DEF(DS_CPL, 0x00000001, 0, CPU_REG_ECX, 4)=0A= > + FEAT_DEF(VMX, 0x00000001, 0, CPU_REG_ECX, 5)=0A= > + FEAT_DEF(SMX, 0x00000001, 0, CPU_REG_ECX, 6)=0A= > + FEAT_DEF(EIST, 0x00000001, 0, CPU_REG_ECX, 7)=0A= > + FEAT_DEF(TM2, 0x00000001, 0, CPU_REG_ECX, 8)=0A= > + FEAT_DEF(SSSE3, 0x00000001, 0, CPU_REG_ECX, 9)=0A= > + FEAT_DEF(CNXT_ID, 0x00000001, 0, CPU_REG_ECX, 10)=0A= > + FEAT_DEF(FMA, 0x00000001, 0, CPU_REG_ECX, 12)=0A= > + FEAT_DEF(CMPXCHG16B, 0x00000001, 0, CPU_REG_ECX, 13)=0A= > + FEAT_DEF(XTPR, 0x00000001, 0, CPU_REG_ECX, 14)=0A= > + FEAT_DEF(PDCM, 0x00000001, 0, CPU_REG_ECX, 15)=0A= > + FEAT_DEF(PCID, 0x00000001, 0, CPU_REG_ECX, 17)=0A= > + FEAT_DEF(DCA, 0x00000001, 0, CPU_REG_ECX, 18)=0A= > + FEAT_DEF(SSE4_1, 0x00000001, 0, CPU_REG_ECX, 19)=0A= > + FEAT_DEF(SSE4_2, 0x00000001, 0, CPU_REG_ECX, 20)=0A= > + FEAT_DEF(X2APIC, 0x00000001, 0, CPU_REG_ECX, 21)=0A= > + FEAT_DEF(MOVBE, 0x00000001, 0, CPU_REG_ECX, 22)=0A= > + FEAT_DEF(POPCNT, 0x00000001, 0, CPU_REG_ECX, 23)=0A= > + FEAT_DEF(TSC_DEADLINE, 0x00000001, 0, CPU_REG_ECX, 24)=0A= > + FEAT_DEF(AES, 0x00000001, 0, CPU_REG_ECX, 25)=0A= > + FEAT_DEF(XSAVE, 0x00000001, 0, CPU_REG_ECX, 26)=0A= > + FEAT_DEF(OSXSAVE, 0x00000001, 0, CPU_REG_ECX, 27)=0A= > + FEAT_DEF(AVX, 0x00000001, 0, CPU_REG_ECX, 28)=0A= > + FEAT_DEF(F16C, 0x00000001, 0, CPU_REG_ECX, 29)=0A= > + FEAT_DEF(RDRAND, 0x00000001, 0, CPU_REG_ECX, 30)=0A= > +=0A= > + FEAT_DEF(FPU, 0x00000001, 0, CPU_REG_EDX, 0)=0A= > + FEAT_DEF(VME, 0x00000001, 0, CPU_REG_EDX, 1)=0A= > + FEAT_DEF(DE, 0x00000001, 0, CPU_REG_EDX, 2)=0A= > + FEAT_DEF(PSE, 0x00000001, 0, CPU_REG_EDX, 3)=0A= > + FEAT_DEF(TSC, 0x00000001, 0, CPU_REG_EDX, 4)=0A= > + FEAT_DEF(MSR, 0x00000001, 0, CPU_REG_EDX, 5)=0A= > + FEAT_DEF(PAE, 0x00000001, 0, CPU_REG_EDX, 6)=0A= > + FEAT_DEF(MCE, 0x00000001, 0, CPU_REG_EDX, 7)=0A= > + FEAT_DEF(CX8, 0x00000001, 0, CPU_REG_EDX, 8)=0A= > + FEAT_DEF(APIC, 0x00000001, 0, CPU_REG_EDX, 9)=0A= > + FEAT_DEF(SEP, 0x00000001, 0, CPU_REG_EDX, 11)=0A= > + FEAT_DEF(MTRR, 0x00000001, 0, CPU_REG_EDX, 12)=0A= > + FEAT_DEF(PGE, 0x00000001, 0, CPU_REG_EDX, 13)=0A= > + FEAT_DEF(MCA, 0x00000001, 0, CPU_REG_EDX, 14)=0A= > + FEAT_DEF(CMOV, 0x00000001, 0, CPU_REG_EDX, 15)=0A= > + FEAT_DEF(PAT, 0x00000001, 0, CPU_REG_EDX, 16)=0A= > + FEAT_DEF(PSE36, 0x00000001, 0, CPU_REG_EDX, 17)=0A= > + FEAT_DEF(PSN, 0x00000001, 0, CPU_REG_EDX, 18)=0A= > + FEAT_DEF(CLFSH, 0x00000001, 0, CPU_REG_EDX, 19)=0A= > + FEAT_DEF(DS, 0x00000001, 0, CPU_REG_EDX, 21)=0A= > + FEAT_DEF(ACPI, 0x00000001, 0, CPU_REG_EDX, 22)=0A= > + FEAT_DEF(MMX, 0x00000001, 0, CPU_REG_EDX, 23)=0A= > + FEAT_DEF(FXSR, 0x00000001, 0, CPU_REG_EDX, 24)=0A= > + FEAT_DEF(SSE, 0x00000001, 0, CPU_REG_EDX, 25)=0A= > + FEAT_DEF(SSE2, 0x00000001, 0, CPU_REG_EDX, 26)=0A= > + FEAT_DEF(SS, 0x00000001, 0, CPU_REG_EDX, 27)=0A= > + FEAT_DEF(HTT, 0x00000001, 0, CPU_REG_EDX, 28)=0A= > + FEAT_DEF(TM, 0x00000001, 0, CPU_REG_EDX, 29)=0A= > + FEAT_DEF(PBE, 0x00000001, 0, CPU_REG_EDX, 31)=0A= > +=0A= > + FEAT_DEF(DIGTEMP, 0x00000006, 0, CPU_REG_EAX, 0)=0A= > + FEAT_DEF(TRBOBST, 0x00000006, 0, CPU_REG_EAX, 1)=0A= > + FEAT_DEF(ARAT, 0x00000006, 0, CPU_REG_EAX, 2)=0A= > + FEAT_DEF(PLN, 0x00000006, 0, CPU_REG_EAX, 4)=0A= > + FEAT_DEF(ECMD, 0x00000006, 0, CPU_REG_EAX, 5)=0A= > + FEAT_DEF(PTM, 0x00000006, 0, CPU_REG_EAX, 6)=0A= > +=0A= > + FEAT_DEF(MPERF_APERF_MSR, 0x00000006, 0, CPU_REG_ECX, 0)=0A= > + FEAT_DEF(ACNT2, 0x00000006, 0, CPU_REG_ECX, 1)=0A= > + FEAT_DEF(ENERGY_EFF, 0x00000006, 0, CPU_REG_ECX, 3)=0A= > +=0A= > + FEAT_DEF(FSGSBASE, 0x00000007, 0, CPU_REG_EBX, 0)=0A= > + FEAT_DEF(BMI1, 0x00000007, 0, CPU_REG_EBX, 2)=0A= > + FEAT_DEF(HLE, 0x00000007, 0, CPU_REG_EBX, 4)=0A= > + FEAT_DEF(AVX2, 0x00000007, 0, CPU_REG_EBX, 5)=0A= > + FEAT_DEF(SMEP, 0x00000007, 0, CPU_REG_EBX, 6)=0A= > + FEAT_DEF(BMI2, 0x00000007, 0, CPU_REG_EBX, 7)=0A= > + FEAT_DEF(ERMS, 0x00000007, 0, CPU_REG_EBX, 8)=0A= > + FEAT_DEF(INVPCID, 0x00000007, 0, CPU_REG_EBX, 10)=0A= > + FEAT_DEF(RTM, 0x00000007, 0, CPU_REG_EBX, 11)=0A= > +=0A= > + FEAT_DEF(LAHF_SAHF, 0x80000001, 0, CPU_REG_ECX, 0)=0A= > + FEAT_DEF(LZCNT, 0x80000001, 0, CPU_REG_ECX, 4)=0A= > +=0A= > + FEAT_DEF(SYSCALL, 0x80000001, 0, CPU_REG_EDX, 11)=0A= > + FEAT_DEF(XD, 0x80000001, 0, CPU_REG_EDX, 20)=0A= > + FEAT_DEF(1GB_PG, 0x80000001, 0, CPU_REG_EDX, 26)=0A= > + FEAT_DEF(RDTSCP, 0x80000001, 0, CPU_REG_EDX, 27)=0A= > + FEAT_DEF(EM64T, 0x80000001, 0, CPU_REG_EDX, 29)=0A= > +=0A= > + FEAT_DEF(INVTSC, 0x80000007, 0, CPU_REG_EDX, 8)=0A= > };=0A= > =0A= > static inline void=0A= > @@ -257,18 +257,18 @@ rte_cpu_get_features(uint32_t leaf, uint32_t sublea= f, cpuid_registers_t out)=0A= > #if defined(__i386__) && defined(__PIC__)=0A= > /* %ebx is a forbidden register if we compile with -fPIC or -fPIE */= =0A= > asm volatile("movl %%ebx,%0 ; cpuid ; xchgl %%ebx,%0"=0A= > - : "=3Dr" (out[REG_EBX]),=0A= > - "=3Da" (out[REG_EAX]),=0A= > - "=3Dc" (out[REG_ECX]),=0A= > - "=3Dd" (out[REG_EDX])=0A= > + : "=3Dr" (out[CPU_REG_EBX]),=0A= > + "=3Da" (out[CPU_REG_EAX]),=0A= > + "=3Dc" (out[CPU_REG_ECX]),=0A= > + "=3Dd" (out[CPU_REG_EDX])=0A= > : "a" (leaf), "c" (subleaf));=0A= > #else=0A= > =0A= > asm volatile("cpuid"=0A= > - : "=3Da" (out[REG_EAX]),=0A= > - "=3Db" (out[REG_EBX]),=0A= > - "=3Dc" (out[REG_ECX]),=0A= > - "=3Dd" (out[REG_EDX])=0A= > + : "=3Da" (out[CPU_REG_EAX]),=0A= > + "=3Db" (out[CPU_REG_EBX]),=0A= > + "=3Dc" (out[CPU_REG_ECX]),=0A= > + "=3Dd" (out[CPU_REG_EDX])=0A= > : "a" (leaf), "c" (subleaf));=0A= > =0A= > #endif=0A= > @@ -292,8 +292,8 @@ rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)= =0A= > return -EFAULT;=0A= > =0A= > rte_cpu_get_features(feat->leaf & 0xffff0000, 0, regs);=0A= > - if (((regs[REG_EAX] ^ feat->leaf) & 0xffff0000) ||=0A= > - regs[REG_EAX] < feat->leaf)=0A= > + if (((regs[CPU_REG_EAX] ^ feat->leaf) & 0xffff0000) ||=0A= > + regs[CPU_REG_EAX] < feat->leaf)=0A= > return 0;=0A= > =0A= > /* get the cpuid leaf containing the desired feature */=0A= =0A=