[dpdk-dev] [PATCH 0/3] dpdk2.0-rc1 build error fix

[dpdk-dev] [PATCH 0/3] dpdk2.0-rc1 build error fix

[Michael Qiu]

This patch set is to fix dpdk2.0-rc1 compile error.

Michael Qiu (3):
  librte_hash: Fix unsupported instruction `crc32' in i686 platform
  app/test: Fix size_t printf formart issue
  librte_eal/common: Fix redeclaration of enumerator ‘REG_EAX’

 app/test/test_hash.c                               |   2 +-
 .../common/include/arch/x86/rte_cpuflags.h         | 210 ++++++++++-----------
 lib/librte_hash/rte_hash_crc.h                     |   4 +
 3 files changed, 110 insertions(+), 106 deletions(-)

-- 
1.9.3

[dpdk-dev] [PATCH 1/3] librte_hash: Fix unsupported instruction `crc32' in i686 platform

[Michael Qiu]

CC rte_hash.o
Error: unsupported instruction `crc32'

The root cause is that i686 platform does not support 'crc32q'
Need make it only available in x86_64 platform

Signed-off-by: Michael Qiu <michael.qiu@intel.com>
---
 lib/librte_hash/rte_hash_crc.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/lib/librte_hash/rte_hash_crc.h b/lib/librte_hash/rte_hash_crc.h
index d28bb2a..4e9546f 100644
--- a/lib/librte_hash/rte_hash_crc.h
+++ b/lib/librte_hash/rte_hash_crc.h
@@ -374,6 +374,7 @@ crc32c_sse42_u32(uint32_t data, uint32_t init_val)
 	return init_val;
 }
 
+#ifdef RTE_ARCH_X86_64
 static inline uint32_t
 crc32c_sse42_u64(uint64_t data, uint64_t init_val)
 {
@@ -383,6 +384,7 @@ crc32c_sse42_u64(uint64_t data, uint64_t init_val)
 			: [data] "rm" (data));
 	return init_val;
 }
+#endif
 
 static inline uint32_t
 crc32c_sse42_u64_mimic(uint64_t data, uint64_t init_val)
@@ -476,8 +478,10 @@ rte_hash_crc_4byte(uint32_t data, uint32_t init_val)
 static inline uint32_t
 rte_hash_crc_8byte(uint64_t data, uint32_t init_val)
 {
+#ifdef RTE_ARCH_X86_64
 	if (likely(crc32_alg == CRC32_SSE42_x64))
 		return crc32c_sse42_u64(data, init_val);
+#endif
 
 	if (likely(crc32_alg & CRC32_SSE42))
 		return crc32c_sse42_u64_mimic(data, init_val);
-- 
1.9.3

[dpdk-dev] [PATCH 2/3] app/test: Fix size_t printf formart issue

[Michael Qiu]

test_hash.c: In function ‘test_crc32_hash_alg_equiv’:
error: format ‘%lu’ expects argument of type ‘long unsigned int’,
but argument 2 has type ‘size_t’ [-Werror=format]

According to C99, for size_t type should use formart "%zu"

Signed-off-by: Michael Qiu <michael.qiu@intel.com>
---
 app/test/test_hash.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/app/test/test_hash.c b/app/test/test_hash.c
index 653dd86..c489b8b 100644
--- a/app/test/test_hash.c
+++ b/app/test/test_hash.c
@@ -226,7 +226,7 @@ test_crc32_hash_alg_equiv(void)
 	if (i == CRC32_ITERATIONS)
 		return 0;
 
-	printf("Failed test data (hex, %lu bytes total):\n", data_len);
+	printf("Failed test data (hex, %zu bytes total):\n", data_len);
 	for (j = 0; j < data_len; j++)
 		printf("%02X%c", ((uint8_t *)data64)[j],
 				((j+1) % 16 == 0 || j == data_len - 1) ? '\n' : ' ');
-- 
1.9.3

[dpdk-dev] [PATCH 3/3] librte_eal/common: Fix redeclaration of enumerator ‘REG_EAX’

[Michael Qiu]

include/rte_cpuflags.h:154:2: error: redeclaration of enumerator ‘REG_EAX’
In file included from /usr/include/signal.h:358:0,
                 from /usr/include/sys/wait.h:30,
                 from /root/dpdk/app/test/test_mp_secondary.c:50:
/usr/include/sys/ucontext.h:180:3: note: previous definition of ‘REG_EAX’ was here

In i686, from REG_EAX to REG_EDX are all defined in
	/usr/include/sys/ucontext.h

Rename to CPU_REG_EAX to avoid this issue.

Signed-off-by: Michael Qou <michael.qiu@intel.com>
---
 .../common/include/arch/x86/rte_cpuflags.h         | 210 ++++++++++-----------
 1 file changed, 105 insertions(+), 105 deletions(-)

diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
index a58dd7b..f367b91 100644
--- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
+++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
@@ -151,104 +151,104 @@ enum rte_cpu_flag_t {
 };
 
 enum cpu_register_t {
-	REG_EAX = 0,
-	REG_EBX,
-	REG_ECX,
-	REG_EDX,
+	CPU_REG_EAX = 0,
+	CPU_REG_EBX,
+	CPU_REG_ECX,
+	CPU_REG_EDX,
 };
 
 static const struct feature_entry cpu_feature_table[] = {
-	FEAT_DEF(SSE3, 0x00000001, 0, REG_ECX,  0)
-	FEAT_DEF(PCLMULQDQ, 0x00000001, 0, REG_ECX,  1)
-	FEAT_DEF(DTES64, 0x00000001, 0, REG_ECX,  2)
-	FEAT_DEF(MONITOR, 0x00000001, 0, REG_ECX,  3)
-	FEAT_DEF(DS_CPL, 0x00000001, 0, REG_ECX,  4)
-	FEAT_DEF(VMX, 0x00000001, 0, REG_ECX,  5)
-	FEAT_DEF(SMX, 0x00000001, 0, REG_ECX,  6)
-	FEAT_DEF(EIST, 0x00000001, 0, REG_ECX,  7)
-	FEAT_DEF(TM2, 0x00000001, 0, REG_ECX,  8)
-	FEAT_DEF(SSSE3, 0x00000001, 0, REG_ECX,  9)
-	FEAT_DEF(CNXT_ID, 0x00000001, 0, REG_ECX, 10)
-	FEAT_DEF(FMA, 0x00000001, 0, REG_ECX, 12)
-	FEAT_DEF(CMPXCHG16B, 0x00000001, 0, REG_ECX, 13)
-	FEAT_DEF(XTPR, 0x00000001, 0, REG_ECX, 14)
-	FEAT_DEF(PDCM, 0x00000001, 0, REG_ECX, 15)
-	FEAT_DEF(PCID, 0x00000001, 0, REG_ECX, 17)
-	FEAT_DEF(DCA, 0x00000001, 0, REG_ECX, 18)
-	FEAT_DEF(SSE4_1, 0x00000001, 0, REG_ECX, 19)
-	FEAT_DEF(SSE4_2, 0x00000001, 0, REG_ECX, 20)
-	FEAT_DEF(X2APIC, 0x00000001, 0, REG_ECX, 21)
-	FEAT_DEF(MOVBE, 0x00000001, 0, REG_ECX, 22)
-	FEAT_DEF(POPCNT, 0x00000001, 0, REG_ECX, 23)
-	FEAT_DEF(TSC_DEADLINE, 0x00000001, 0, REG_ECX, 24)
-	FEAT_DEF(AES, 0x00000001, 0, REG_ECX, 25)
-	FEAT_DEF(XSAVE, 0x00000001, 0, REG_ECX, 26)
-	FEAT_DEF(OSXSAVE, 0x00000001, 0, REG_ECX, 27)
-	FEAT_DEF(AVX, 0x00000001, 0, REG_ECX, 28)
-	FEAT_DEF(F16C, 0x00000001, 0, REG_ECX, 29)
-	FEAT_DEF(RDRAND, 0x00000001, 0, REG_ECX, 30)
-
-	FEAT_DEF(FPU, 0x00000001, 0, REG_EDX,  0)
-	FEAT_DEF(VME, 0x00000001, 0, REG_EDX,  1)
-	FEAT_DEF(DE, 0x00000001, 0, REG_EDX,  2)
-	FEAT_DEF(PSE, 0x00000001, 0, REG_EDX,  3)
-	FEAT_DEF(TSC, 0x00000001, 0, REG_EDX,  4)
-	FEAT_DEF(MSR, 0x00000001, 0, REG_EDX,  5)
-	FEAT_DEF(PAE, 0x00000001, 0, REG_EDX,  6)
-	FEAT_DEF(MCE, 0x00000001, 0, REG_EDX,  7)
-	FEAT_DEF(CX8, 0x00000001, 0, REG_EDX,  8)
-	FEAT_DEF(APIC, 0x00000001, 0, REG_EDX,  9)
-	FEAT_DEF(SEP, 0x00000001, 0, REG_EDX, 11)
-	FEAT_DEF(MTRR, 0x00000001, 0, REG_EDX, 12)
-	FEAT_DEF(PGE, 0x00000001, 0, REG_EDX, 13)
-	FEAT_DEF(MCA, 0x00000001, 0, REG_EDX, 14)
-	FEAT_DEF(CMOV, 0x00000001, 0, REG_EDX, 15)
-	FEAT_DEF(PAT, 0x00000001, 0, REG_EDX, 16)
-	FEAT_DEF(PSE36, 0x00000001, 0, REG_EDX, 17)
-	FEAT_DEF(PSN, 0x00000001, 0, REG_EDX, 18)
-	FEAT_DEF(CLFSH, 0x00000001, 0, REG_EDX, 19)
-	FEAT_DEF(DS, 0x00000001, 0, REG_EDX, 21)
-	FEAT_DEF(ACPI, 0x00000001, 0, REG_EDX, 22)
-	FEAT_DEF(MMX, 0x00000001, 0, REG_EDX, 23)
-	FEAT_DEF(FXSR, 0x00000001, 0, REG_EDX, 24)
-	FEAT_DEF(SSE, 0x00000001, 0, REG_EDX, 25)
-	FEAT_DEF(SSE2, 0x00000001, 0, REG_EDX, 26)
-	FEAT_DEF(SS, 0x00000001, 0, REG_EDX, 27)
-	FEAT_DEF(HTT, 0x00000001, 0, REG_EDX, 28)
-	FEAT_DEF(TM, 0x00000001, 0, REG_EDX, 29)
-	FEAT_DEF(PBE, 0x00000001, 0, REG_EDX, 31)
-
-	FEAT_DEF(DIGTEMP, 0x00000006, 0, REG_EAX,  0)
-	FEAT_DEF(TRBOBST, 0x00000006, 0, REG_EAX,  1)
-	FEAT_DEF(ARAT, 0x00000006, 0, REG_EAX,  2)
-	FEAT_DEF(PLN, 0x00000006, 0, REG_EAX,  4)
-	FEAT_DEF(ECMD, 0x00000006, 0, REG_EAX,  5)
-	FEAT_DEF(PTM, 0x00000006, 0, REG_EAX,  6)
-
-	FEAT_DEF(MPERF_APERF_MSR, 0x00000006, 0, REG_ECX,  0)
-	FEAT_DEF(ACNT2, 0x00000006, 0, REG_ECX,  1)
-	FEAT_DEF(ENERGY_EFF, 0x00000006, 0, REG_ECX,  3)
-
-	FEAT_DEF(FSGSBASE, 0x00000007, 0, REG_EBX,  0)
-	FEAT_DEF(BMI1, 0x00000007, 0, REG_EBX,  2)
-	FEAT_DEF(HLE, 0x00000007, 0, REG_EBX,  4)
-	FEAT_DEF(AVX2, 0x00000007, 0, REG_EBX,  5)
-	FEAT_DEF(SMEP, 0x00000007, 0, REG_EBX,  6)
-	FEAT_DEF(BMI2, 0x00000007, 0, REG_EBX,  7)
-	FEAT_DEF(ERMS, 0x00000007, 0, REG_EBX,  8)
-	FEAT_DEF(INVPCID, 0x00000007, 0, REG_EBX, 10)
-	FEAT_DEF(RTM, 0x00000007, 0, REG_EBX, 11)
-
-	FEAT_DEF(LAHF_SAHF, 0x80000001, 0, REG_ECX,  0)
-	FEAT_DEF(LZCNT, 0x80000001, 0, REG_ECX,  4)
-
-	FEAT_DEF(SYSCALL, 0x80000001, 0, REG_EDX, 11)
-	FEAT_DEF(XD, 0x80000001, 0, REG_EDX, 20)
-	FEAT_DEF(1GB_PG, 0x80000001, 0, REG_EDX, 26)
-	FEAT_DEF(RDTSCP, 0x80000001, 0, REG_EDX, 27)
-	FEAT_DEF(EM64T, 0x80000001, 0, REG_EDX, 29)
-
-	FEAT_DEF(INVTSC, 0x80000007, 0, REG_EDX,  8)
+	FEAT_DEF(SSE3, 0x00000001, 0, CPU_REG_ECX,  0)
+	FEAT_DEF(PCLMULQDQ, 0x00000001, 0, CPU_REG_ECX,  1)
+	FEAT_DEF(DTES64, 0x00000001, 0, CPU_REG_ECX,  2)
+	FEAT_DEF(MONITOR, 0x00000001, 0, CPU_REG_ECX,  3)
+	FEAT_DEF(DS_CPL, 0x00000001, 0, CPU_REG_ECX,  4)
+	FEAT_DEF(VMX, 0x00000001, 0, CPU_REG_ECX,  5)
+	FEAT_DEF(SMX, 0x00000001, 0, CPU_REG_ECX,  6)
+	FEAT_DEF(EIST, 0x00000001, 0, CPU_REG_ECX,  7)
+	FEAT_DEF(TM2, 0x00000001, 0, CPU_REG_ECX,  8)
+	FEAT_DEF(SSSE3, 0x00000001, 0, CPU_REG_ECX,  9)
+	FEAT_DEF(CNXT_ID, 0x00000001, 0, CPU_REG_ECX, 10)
+	FEAT_DEF(FMA, 0x00000001, 0, CPU_REG_ECX, 12)
+	FEAT_DEF(CMPXCHG16B, 0x00000001, 0, CPU_REG_ECX, 13)
+	FEAT_DEF(XTPR, 0x00000001, 0, CPU_REG_ECX, 14)
+	FEAT_DEF(PDCM, 0x00000001, 0, CPU_REG_ECX, 15)
+	FEAT_DEF(PCID, 0x00000001, 0, CPU_REG_ECX, 17)
+	FEAT_DEF(DCA, 0x00000001, 0, CPU_REG_ECX, 18)
+	FEAT_DEF(SSE4_1, 0x00000001, 0, CPU_REG_ECX, 19)
+	FEAT_DEF(SSE4_2, 0x00000001, 0, CPU_REG_ECX, 20)
+	FEAT_DEF(X2APIC, 0x00000001, 0, CPU_REG_ECX, 21)
+	FEAT_DEF(MOVBE, 0x00000001, 0, CPU_REG_ECX, 22)
+	FEAT_DEF(POPCNT, 0x00000001, 0, CPU_REG_ECX, 23)
+	FEAT_DEF(TSC_DEADLINE, 0x00000001, 0, CPU_REG_ECX, 24)
+	FEAT_DEF(AES, 0x00000001, 0, CPU_REG_ECX, 25)
+	FEAT_DEF(XSAVE, 0x00000001, 0, CPU_REG_ECX, 26)
+	FEAT_DEF(OSXSAVE, 0x00000001, 0, CPU_REG_ECX, 27)
+	FEAT_DEF(AVX, 0x00000001, 0, CPU_REG_ECX, 28)
+	FEAT_DEF(F16C, 0x00000001, 0, CPU_REG_ECX, 29)
+	FEAT_DEF(RDRAND, 0x00000001, 0, CPU_REG_ECX, 30)
+
+	FEAT_DEF(FPU, 0x00000001, 0, CPU_REG_EDX,  0)
+	FEAT_DEF(VME, 0x00000001, 0, CPU_REG_EDX,  1)
+	FEAT_DEF(DE, 0x00000001, 0, CPU_REG_EDX,  2)
+	FEAT_DEF(PSE, 0x00000001, 0, CPU_REG_EDX,  3)
+	FEAT_DEF(TSC, 0x00000001, 0, CPU_REG_EDX,  4)
+	FEAT_DEF(MSR, 0x00000001, 0, CPU_REG_EDX,  5)
+	FEAT_DEF(PAE, 0x00000001, 0, CPU_REG_EDX,  6)
+	FEAT_DEF(MCE, 0x00000001, 0, CPU_REG_EDX,  7)
+	FEAT_DEF(CX8, 0x00000001, 0, CPU_REG_EDX,  8)
+	FEAT_DEF(APIC, 0x00000001, 0, CPU_REG_EDX,  9)
+	FEAT_DEF(SEP, 0x00000001, 0, CPU_REG_EDX, 11)
+	FEAT_DEF(MTRR, 0x00000001, 0, CPU_REG_EDX, 12)
+	FEAT_DEF(PGE, 0x00000001, 0, CPU_REG_EDX, 13)
+	FEAT_DEF(MCA, 0x00000001, 0, CPU_REG_EDX, 14)
+	FEAT_DEF(CMOV, 0x00000001, 0, CPU_REG_EDX, 15)
+	FEAT_DEF(PAT, 0x00000001, 0, CPU_REG_EDX, 16)
+	FEAT_DEF(PSE36, 0x00000001, 0, CPU_REG_EDX, 17)
+	FEAT_DEF(PSN, 0x00000001, 0, CPU_REG_EDX, 18)
+	FEAT_DEF(CLFSH, 0x00000001, 0, CPU_REG_EDX, 19)
+	FEAT_DEF(DS, 0x00000001, 0, CPU_REG_EDX, 21)
+	FEAT_DEF(ACPI, 0x00000001, 0, CPU_REG_EDX, 22)
+	FEAT_DEF(MMX, 0x00000001, 0, CPU_REG_EDX, 23)
+	FEAT_DEF(FXSR, 0x00000001, 0, CPU_REG_EDX, 24)
+	FEAT_DEF(SSE, 0x00000001, 0, CPU_REG_EDX, 25)
+	FEAT_DEF(SSE2, 0x00000001, 0, CPU_REG_EDX, 26)
+	FEAT_DEF(SS, 0x00000001, 0, CPU_REG_EDX, 27)
+	FEAT_DEF(HTT, 0x00000001, 0, CPU_REG_EDX, 28)
+	FEAT_DEF(TM, 0x00000001, 0, CPU_REG_EDX, 29)
+	FEAT_DEF(PBE, 0x00000001, 0, CPU_REG_EDX, 31)
+
+	FEAT_DEF(DIGTEMP, 0x00000006, 0, CPU_REG_EAX,  0)
+	FEAT_DEF(TRBOBST, 0x00000006, 0, CPU_REG_EAX,  1)
+	FEAT_DEF(ARAT, 0x00000006, 0, CPU_REG_EAX,  2)
+	FEAT_DEF(PLN, 0x00000006, 0, CPU_REG_EAX,  4)
+	FEAT_DEF(ECMD, 0x00000006, 0, CPU_REG_EAX,  5)
+	FEAT_DEF(PTM, 0x00000006, 0, CPU_REG_EAX,  6)
+
+	FEAT_DEF(MPERF_APERF_MSR, 0x00000006, 0, CPU_REG_ECX,  0)
+	FEAT_DEF(ACNT2, 0x00000006, 0, CPU_REG_ECX,  1)
+	FEAT_DEF(ENERGY_EFF, 0x00000006, 0, CPU_REG_ECX,  3)
+
+	FEAT_DEF(FSGSBASE, 0x00000007, 0, CPU_REG_EBX,  0)
+	FEAT_DEF(BMI1, 0x00000007, 0, CPU_REG_EBX,  2)
+	FEAT_DEF(HLE, 0x00000007, 0, CPU_REG_EBX,  4)
+	FEAT_DEF(AVX2, 0x00000007, 0, CPU_REG_EBX,  5)
+	FEAT_DEF(SMEP, 0x00000007, 0, CPU_REG_EBX,  6)
+	FEAT_DEF(BMI2, 0x00000007, 0, CPU_REG_EBX,  7)
+	FEAT_DEF(ERMS, 0x00000007, 0, CPU_REG_EBX,  8)
+	FEAT_DEF(INVPCID, 0x00000007, 0, CPU_REG_EBX, 10)
+	FEAT_DEF(RTM, 0x00000007, 0, CPU_REG_EBX, 11)
+
+	FEAT_DEF(LAHF_SAHF, 0x80000001, 0, CPU_REG_ECX,  0)
+	FEAT_DEF(LZCNT, 0x80000001, 0, CPU_REG_ECX,  4)
+
+	FEAT_DEF(SYSCALL, 0x80000001, 0, CPU_REG_EDX, 11)
+	FEAT_DEF(XD, 0x80000001, 0, CPU_REG_EDX, 20)
+	FEAT_DEF(1GB_PG, 0x80000001, 0, CPU_REG_EDX, 26)
+	FEAT_DEF(RDTSCP, 0x80000001, 0, CPU_REG_EDX, 27)
+	FEAT_DEF(EM64T, 0x80000001, 0, CPU_REG_EDX, 29)
+
+	FEAT_DEF(INVTSC, 0x80000007, 0, CPU_REG_EDX,  8)
 };
 
 static inline void
@@ -257,18 +257,18 @@ rte_cpu_get_features(uint32_t leaf, uint32_t subleaf, cpuid_registers_t out)
 #if defined(__i386__) && defined(__PIC__)
     /* %ebx is a forbidden register if we compile with -fPIC or -fPIE */
     asm volatile("movl %%ebx,%0 ; cpuid ; xchgl %%ebx,%0"
-		 : "=r" (out[REG_EBX]),
-		   "=a" (out[REG_EAX]),
-		   "=c" (out[REG_ECX]),
-		   "=d" (out[REG_EDX])
+		 : "=r" (out[CPU_REG_EBX]),
+		   "=a" (out[CPU_REG_EAX]),
+		   "=c" (out[CPU_REG_ECX]),
+		   "=d" (out[CPU_REG_EDX])
 		 : "a" (leaf), "c" (subleaf));
 #else
 
     asm volatile("cpuid"
-		 : "=a" (out[REG_EAX]),
-		   "=b" (out[REG_EBX]),
-		   "=c" (out[REG_ECX]),
-		   "=d" (out[REG_EDX])
+		 : "=a" (out[CPU_REG_EAX]),
+		   "=b" (out[CPU_REG_EBX]),
+		   "=c" (out[CPU_REG_ECX]),
+		   "=d" (out[CPU_REG_EDX])
 		 : "a" (leaf), "c" (subleaf));
 
 #endif
@@ -292,8 +292,8 @@ rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
 		return -EFAULT;
 
 	rte_cpu_get_features(feat->leaf & 0xffff0000, 0, regs);
-	if (((regs[REG_EAX] ^ feat->leaf) & 0xffff0000) ||
-	      regs[REG_EAX] < feat->leaf)
+	if (((regs[CPU_REG_EAX] ^ feat->leaf) & 0xffff0000) ||
+	      regs[CPU_REG_EAX] < feat->leaf)
 		return 0;
 
 	/* get the cpuid leaf containing the desired feature */
-- 
1.9.3

Re: [dpdk-dev] [PATCH 2/3] app/test: Fix size_t printf formart issue

[Bruce Richardson]

On Thu, Mar 05, 2015 at 09:15:38PM +0800, Michael Qiu wrote:
> test_hash.c: In function ‘test_crc32_hash_alg_equiv’:
> error: format ‘%lu’ expects argument of type ‘long unsigned int’,
> but argument 2 has type ‘size_t’ [-Werror=format]
> 
> According to C99, for size_t type should use formart "%zu"
> 
> Signed-off-by: Michael Qiu <michael.qiu@intel.com>

Typo in title. Otherwise
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
> ---
>  app/test/test_hash.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/app/test/test_hash.c b/app/test/test_hash.c
> index 653dd86..c489b8b 100644
> --- a/app/test/test_hash.c
> +++ b/app/test/test_hash.c
> @@ -226,7 +226,7 @@ test_crc32_hash_alg_equiv(void)
>  	if (i == CRC32_ITERATIONS)
>  		return 0;
>  
> -	printf("Failed test data (hex, %lu bytes total):\n", data_len);
> +	printf("Failed test data (hex, %zu bytes total):\n", data_len);
>  	for (j = 0; j < data_len; j++)
>  		printf("%02X%c", ((uint8_t *)data64)[j],
>  				((j+1) % 16 == 0 || j == data_len - 1) ? '\n' : ' ');
> -- 
> 1.9.3
> 

Re: [dpdk-dev] [PATCH 3/3] librte_eal/common: Fix redeclaration of enumerator ‘REG_EAX’

[Bruce Richardson]

On Thu, Mar 05, 2015 at 09:15:39PM +0800, Michael Qiu wrote:
> include/rte_cpuflags.h:154:2: error: redeclaration of enumerator ‘REG_EAX’
> In file included from /usr/include/signal.h:358:0,
>                  from /usr/include/sys/wait.h:30,
>                  from /root/dpdk/app/test/test_mp_secondary.c:50:
> /usr/include/sys/ucontext.h:180:3: note: previous definition of ‘REG_EAX’ was here
> 
> In i686, from REG_EAX to REG_EDX are all defined in
> 	/usr/include/sys/ucontext.h
> 
> Rename to CPU_REG_EAX to avoid this issue.
RTE_ prefix for consistency with other public DPDK symbols perhaps?

/Bruce

> 
> Signed-off-by: Michael Qou <michael.qiu@intel.com>
> ---
>  .../common/include/arch/x86/rte_cpuflags.h         | 210 ++++++++++-----------
>  1 file changed, 105 insertions(+), 105 deletions(-)
> 
> diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
> index a58dd7b..f367b91 100644
> --- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
> +++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
> @@ -151,104 +151,104 @@ enum rte_cpu_flag_t {
>  };
>  
>  enum cpu_register_t {
> -	REG_EAX = 0,
> -	REG_EBX,
> -	REG_ECX,
> -	REG_EDX,
> +	CPU_REG_EAX = 0,
> +	CPU_REG_EBX,
> +	CPU_REG_ECX,
> +	CPU_REG_EDX,
>  };
>  
>  static const struct feature_entry cpu_feature_table[] = {
> -	FEAT_DEF(SSE3, 0x00000001, 0, REG_ECX,  0)
> -	FEAT_DEF(PCLMULQDQ, 0x00000001, 0, REG_ECX,  1)
> -	FEAT_DEF(DTES64, 0x00000001, 0, REG_ECX,  2)
> -	FEAT_DEF(MONITOR, 0x00000001, 0, REG_ECX,  3)
> -	FEAT_DEF(DS_CPL, 0x00000001, 0, REG_ECX,  4)
> -	FEAT_DEF(VMX, 0x00000001, 0, REG_ECX,  5)
> -	FEAT_DEF(SMX, 0x00000001, 0, REG_ECX,  6)
> -	FEAT_DEF(EIST, 0x00000001, 0, REG_ECX,  7)
> -	FEAT_DEF(TM2, 0x00000001, 0, REG_ECX,  8)
> -	FEAT_DEF(SSSE3, 0x00000001, 0, REG_ECX,  9)
> -	FEAT_DEF(CNXT_ID, 0x00000001, 0, REG_ECX, 10)
> -	FEAT_DEF(FMA, 0x00000001, 0, REG_ECX, 12)
> -	FEAT_DEF(CMPXCHG16B, 0x00000001, 0, REG_ECX, 13)
> -	FEAT_DEF(XTPR, 0x00000001, 0, REG_ECX, 14)
> -	FEAT_DEF(PDCM, 0x00000001, 0, REG_ECX, 15)
> -	FEAT_DEF(PCID, 0x00000001, 0, REG_ECX, 17)
> -	FEAT_DEF(DCA, 0x00000001, 0, REG_ECX, 18)
> -	FEAT_DEF(SSE4_1, 0x00000001, 0, REG_ECX, 19)
> -	FEAT_DEF(SSE4_2, 0x00000001, 0, REG_ECX, 20)
> -	FEAT_DEF(X2APIC, 0x00000001, 0, REG_ECX, 21)
> -	FEAT_DEF(MOVBE, 0x00000001, 0, REG_ECX, 22)
> -	FEAT_DEF(POPCNT, 0x00000001, 0, REG_ECX, 23)
> -	FEAT_DEF(TSC_DEADLINE, 0x00000001, 0, REG_ECX, 24)
> -	FEAT_DEF(AES, 0x00000001, 0, REG_ECX, 25)
> -	FEAT_DEF(XSAVE, 0x00000001, 0, REG_ECX, 26)
> -	FEAT_DEF(OSXSAVE, 0x00000001, 0, REG_ECX, 27)
> -	FEAT_DEF(AVX, 0x00000001, 0, REG_ECX, 28)
> -	FEAT_DEF(F16C, 0x00000001, 0, REG_ECX, 29)
> -	FEAT_DEF(RDRAND, 0x00000001, 0, REG_ECX, 30)
> -
> -	FEAT_DEF(FPU, 0x00000001, 0, REG_EDX,  0)
> -	FEAT_DEF(VME, 0x00000001, 0, REG_EDX,  1)
> -	FEAT_DEF(DE, 0x00000001, 0, REG_EDX,  2)
> -	FEAT_DEF(PSE, 0x00000001, 0, REG_EDX,  3)
> -	FEAT_DEF(TSC, 0x00000001, 0, REG_EDX,  4)
> -	FEAT_DEF(MSR, 0x00000001, 0, REG_EDX,  5)
> -	FEAT_DEF(PAE, 0x00000001, 0, REG_EDX,  6)
> -	FEAT_DEF(MCE, 0x00000001, 0, REG_EDX,  7)
> -	FEAT_DEF(CX8, 0x00000001, 0, REG_EDX,  8)
> -	FEAT_DEF(APIC, 0x00000001, 0, REG_EDX,  9)
> -	FEAT_DEF(SEP, 0x00000001, 0, REG_EDX, 11)
> -	FEAT_DEF(MTRR, 0x00000001, 0, REG_EDX, 12)
> -	FEAT_DEF(PGE, 0x00000001, 0, REG_EDX, 13)
> -	FEAT_DEF(MCA, 0x00000001, 0, REG_EDX, 14)
> -	FEAT_DEF(CMOV, 0x00000001, 0, REG_EDX, 15)
> -	FEAT_DEF(PAT, 0x00000001, 0, REG_EDX, 16)
> -	FEAT_DEF(PSE36, 0x00000001, 0, REG_EDX, 17)
> -	FEAT_DEF(PSN, 0x00000001, 0, REG_EDX, 18)
> -	FEAT_DEF(CLFSH, 0x00000001, 0, REG_EDX, 19)
> -	FEAT_DEF(DS, 0x00000001, 0, REG_EDX, 21)
> -	FEAT_DEF(ACPI, 0x00000001, 0, REG_EDX, 22)
> -	FEAT_DEF(MMX, 0x00000001, 0, REG_EDX, 23)
> -	FEAT_DEF(FXSR, 0x00000001, 0, REG_EDX, 24)
> -	FEAT_DEF(SSE, 0x00000001, 0, REG_EDX, 25)
> -	FEAT_DEF(SSE2, 0x00000001, 0, REG_EDX, 26)
> -	FEAT_DEF(SS, 0x00000001, 0, REG_EDX, 27)
> -	FEAT_DEF(HTT, 0x00000001, 0, REG_EDX, 28)
> -	FEAT_DEF(TM, 0x00000001, 0, REG_EDX, 29)
> -	FEAT_DEF(PBE, 0x00000001, 0, REG_EDX, 31)
> -
> -	FEAT_DEF(DIGTEMP, 0x00000006, 0, REG_EAX,  0)
> -	FEAT_DEF(TRBOBST, 0x00000006, 0, REG_EAX,  1)
> -	FEAT_DEF(ARAT, 0x00000006, 0, REG_EAX,  2)
> -	FEAT_DEF(PLN, 0x00000006, 0, REG_EAX,  4)
> -	FEAT_DEF(ECMD, 0x00000006, 0, REG_EAX,  5)
> -	FEAT_DEF(PTM, 0x00000006, 0, REG_EAX,  6)
> -
> -	FEAT_DEF(MPERF_APERF_MSR, 0x00000006, 0, REG_ECX,  0)
> -	FEAT_DEF(ACNT2, 0x00000006, 0, REG_ECX,  1)
> -	FEAT_DEF(ENERGY_EFF, 0x00000006, 0, REG_ECX,  3)
> -
> -	FEAT_DEF(FSGSBASE, 0x00000007, 0, REG_EBX,  0)
> -	FEAT_DEF(BMI1, 0x00000007, 0, REG_EBX,  2)
> -	FEAT_DEF(HLE, 0x00000007, 0, REG_EBX,  4)
> -	FEAT_DEF(AVX2, 0x00000007, 0, REG_EBX,  5)
> -	FEAT_DEF(SMEP, 0x00000007, 0, REG_EBX,  6)
> -	FEAT_DEF(BMI2, 0x00000007, 0, REG_EBX,  7)
> -	FEAT_DEF(ERMS, 0x00000007, 0, REG_EBX,  8)
> -	FEAT_DEF(INVPCID, 0x00000007, 0, REG_EBX, 10)
> -	FEAT_DEF(RTM, 0x00000007, 0, REG_EBX, 11)
> -
> -	FEAT_DEF(LAHF_SAHF, 0x80000001, 0, REG_ECX,  0)
> -	FEAT_DEF(LZCNT, 0x80000001, 0, REG_ECX,  4)
> -
> -	FEAT_DEF(SYSCALL, 0x80000001, 0, REG_EDX, 11)
> -	FEAT_DEF(XD, 0x80000001, 0, REG_EDX, 20)
> -	FEAT_DEF(1GB_PG, 0x80000001, 0, REG_EDX, 26)
> -	FEAT_DEF(RDTSCP, 0x80000001, 0, REG_EDX, 27)
> -	FEAT_DEF(EM64T, 0x80000001, 0, REG_EDX, 29)
> -
> -	FEAT_DEF(INVTSC, 0x80000007, 0, REG_EDX,  8)
> +	FEAT_DEF(SSE3, 0x00000001, 0, CPU_REG_ECX,  0)
> +	FEAT_DEF(PCLMULQDQ, 0x00000001, 0, CPU_REG_ECX,  1)
> +	FEAT_DEF(DTES64, 0x00000001, 0, CPU_REG_ECX,  2)
> +	FEAT_DEF(MONITOR, 0x00000001, 0, CPU_REG_ECX,  3)
> +	FEAT_DEF(DS_CPL, 0x00000001, 0, CPU_REG_ECX,  4)
> +	FEAT_DEF(VMX, 0x00000001, 0, CPU_REG_ECX,  5)
> +	FEAT_DEF(SMX, 0x00000001, 0, CPU_REG_ECX,  6)
> +	FEAT_DEF(EIST, 0x00000001, 0, CPU_REG_ECX,  7)
> +	FEAT_DEF(TM2, 0x00000001, 0, CPU_REG_ECX,  8)
> +	FEAT_DEF(SSSE3, 0x00000001, 0, CPU_REG_ECX,  9)
> +	FEAT_DEF(CNXT_ID, 0x00000001, 0, CPU_REG_ECX, 10)
> +	FEAT_DEF(FMA, 0x00000001, 0, CPU_REG_ECX, 12)
> +	FEAT_DEF(CMPXCHG16B, 0x00000001, 0, CPU_REG_ECX, 13)
> +	FEAT_DEF(XTPR, 0x00000001, 0, CPU_REG_ECX, 14)
> +	FEAT_DEF(PDCM, 0x00000001, 0, CPU_REG_ECX, 15)
> +	FEAT_DEF(PCID, 0x00000001, 0, CPU_REG_ECX, 17)
> +	FEAT_DEF(DCA, 0x00000001, 0, CPU_REG_ECX, 18)
> +	FEAT_DEF(SSE4_1, 0x00000001, 0, CPU_REG_ECX, 19)
> +	FEAT_DEF(SSE4_2, 0x00000001, 0, CPU_REG_ECX, 20)
> +	FEAT_DEF(X2APIC, 0x00000001, 0, CPU_REG_ECX, 21)
> +	FEAT_DEF(MOVBE, 0x00000001, 0, CPU_REG_ECX, 22)
> +	FEAT_DEF(POPCNT, 0x00000001, 0, CPU_REG_ECX, 23)
> +	FEAT_DEF(TSC_DEADLINE, 0x00000001, 0, CPU_REG_ECX, 24)
> +	FEAT_DEF(AES, 0x00000001, 0, CPU_REG_ECX, 25)
> +	FEAT_DEF(XSAVE, 0x00000001, 0, CPU_REG_ECX, 26)
> +	FEAT_DEF(OSXSAVE, 0x00000001, 0, CPU_REG_ECX, 27)
> +	FEAT_DEF(AVX, 0x00000001, 0, CPU_REG_ECX, 28)
> +	FEAT_DEF(F16C, 0x00000001, 0, CPU_REG_ECX, 29)
> +	FEAT_DEF(RDRAND, 0x00000001, 0, CPU_REG_ECX, 30)
> +
> +	FEAT_DEF(FPU, 0x00000001, 0, CPU_REG_EDX,  0)
> +	FEAT_DEF(VME, 0x00000001, 0, CPU_REG_EDX,  1)
> +	FEAT_DEF(DE, 0x00000001, 0, CPU_REG_EDX,  2)
> +	FEAT_DEF(PSE, 0x00000001, 0, CPU_REG_EDX,  3)
> +	FEAT_DEF(TSC, 0x00000001, 0, CPU_REG_EDX,  4)
> +	FEAT_DEF(MSR, 0x00000001, 0, CPU_REG_EDX,  5)
> +	FEAT_DEF(PAE, 0x00000001, 0, CPU_REG_EDX,  6)
> +	FEAT_DEF(MCE, 0x00000001, 0, CPU_REG_EDX,  7)
> +	FEAT_DEF(CX8, 0x00000001, 0, CPU_REG_EDX,  8)
> +	FEAT_DEF(APIC, 0x00000001, 0, CPU_REG_EDX,  9)
> +	FEAT_DEF(SEP, 0x00000001, 0, CPU_REG_EDX, 11)
> +	FEAT_DEF(MTRR, 0x00000001, 0, CPU_REG_EDX, 12)
> +	FEAT_DEF(PGE, 0x00000001, 0, CPU_REG_EDX, 13)
> +	FEAT_DEF(MCA, 0x00000001, 0, CPU_REG_EDX, 14)
> +	FEAT_DEF(CMOV, 0x00000001, 0, CPU_REG_EDX, 15)
> +	FEAT_DEF(PAT, 0x00000001, 0, CPU_REG_EDX, 16)
> +	FEAT_DEF(PSE36, 0x00000001, 0, CPU_REG_EDX, 17)
> +	FEAT_DEF(PSN, 0x00000001, 0, CPU_REG_EDX, 18)
> +	FEAT_DEF(CLFSH, 0x00000001, 0, CPU_REG_EDX, 19)
> +	FEAT_DEF(DS, 0x00000001, 0, CPU_REG_EDX, 21)
> +	FEAT_DEF(ACPI, 0x00000001, 0, CPU_REG_EDX, 22)
> +	FEAT_DEF(MMX, 0x00000001, 0, CPU_REG_EDX, 23)
> +	FEAT_DEF(FXSR, 0x00000001, 0, CPU_REG_EDX, 24)
> +	FEAT_DEF(SSE, 0x00000001, 0, CPU_REG_EDX, 25)
> +	FEAT_DEF(SSE2, 0x00000001, 0, CPU_REG_EDX, 26)
> +	FEAT_DEF(SS, 0x00000001, 0, CPU_REG_EDX, 27)
> +	FEAT_DEF(HTT, 0x00000001, 0, CPU_REG_EDX, 28)
> +	FEAT_DEF(TM, 0x00000001, 0, CPU_REG_EDX, 29)
> +	FEAT_DEF(PBE, 0x00000001, 0, CPU_REG_EDX, 31)
> +
> +	FEAT_DEF(DIGTEMP, 0x00000006, 0, CPU_REG_EAX,  0)
> +	FEAT_DEF(TRBOBST, 0x00000006, 0, CPU_REG_EAX,  1)
> +	FEAT_DEF(ARAT, 0x00000006, 0, CPU_REG_EAX,  2)
> +	FEAT_DEF(PLN, 0x00000006, 0, CPU_REG_EAX,  4)
> +	FEAT_DEF(ECMD, 0x00000006, 0, CPU_REG_EAX,  5)
> +	FEAT_DEF(PTM, 0x00000006, 0, CPU_REG_EAX,  6)
> +
> +	FEAT_DEF(MPERF_APERF_MSR, 0x00000006, 0, CPU_REG_ECX,  0)
> +	FEAT_DEF(ACNT2, 0x00000006, 0, CPU_REG_ECX,  1)
> +	FEAT_DEF(ENERGY_EFF, 0x00000006, 0, CPU_REG_ECX,  3)
> +
> +	FEAT_DEF(FSGSBASE, 0x00000007, 0, CPU_REG_EBX,  0)
> +	FEAT_DEF(BMI1, 0x00000007, 0, CPU_REG_EBX,  2)
> +	FEAT_DEF(HLE, 0x00000007, 0, CPU_REG_EBX,  4)
> +	FEAT_DEF(AVX2, 0x00000007, 0, CPU_REG_EBX,  5)
> +	FEAT_DEF(SMEP, 0x00000007, 0, CPU_REG_EBX,  6)
> +	FEAT_DEF(BMI2, 0x00000007, 0, CPU_REG_EBX,  7)
> +	FEAT_DEF(ERMS, 0x00000007, 0, CPU_REG_EBX,  8)
> +	FEAT_DEF(INVPCID, 0x00000007, 0, CPU_REG_EBX, 10)
> +	FEAT_DEF(RTM, 0x00000007, 0, CPU_REG_EBX, 11)
> +
> +	FEAT_DEF(LAHF_SAHF, 0x80000001, 0, CPU_REG_ECX,  0)
> +	FEAT_DEF(LZCNT, 0x80000001, 0, CPU_REG_ECX,  4)
> +
> +	FEAT_DEF(SYSCALL, 0x80000001, 0, CPU_REG_EDX, 11)
> +	FEAT_DEF(XD, 0x80000001, 0, CPU_REG_EDX, 20)
> +	FEAT_DEF(1GB_PG, 0x80000001, 0, CPU_REG_EDX, 26)
> +	FEAT_DEF(RDTSCP, 0x80000001, 0, CPU_REG_EDX, 27)
> +	FEAT_DEF(EM64T, 0x80000001, 0, CPU_REG_EDX, 29)
> +
> +	FEAT_DEF(INVTSC, 0x80000007, 0, CPU_REG_EDX,  8)
>  };
>  
>  static inline void
> @@ -257,18 +257,18 @@ rte_cpu_get_features(uint32_t leaf, uint32_t subleaf, cpuid_registers_t out)
>  #if defined(__i386__) && defined(__PIC__)
>      /* %ebx is a forbidden register if we compile with -fPIC or -fPIE */
>      asm volatile("movl %%ebx,%0 ; cpuid ; xchgl %%ebx,%0"
> -		 : "=r" (out[REG_EBX]),
> -		   "=a" (out[REG_EAX]),
> -		   "=c" (out[REG_ECX]),
> -		   "=d" (out[REG_EDX])
> +		 : "=r" (out[CPU_REG_EBX]),
> +		   "=a" (out[CPU_REG_EAX]),
> +		   "=c" (out[CPU_REG_ECX]),
> +		   "=d" (out[CPU_REG_EDX])
>  		 : "a" (leaf), "c" (subleaf));
>  #else
>  
>      asm volatile("cpuid"
> -		 : "=a" (out[REG_EAX]),
> -		   "=b" (out[REG_EBX]),
> -		   "=c" (out[REG_ECX]),
> -		   "=d" (out[REG_EDX])
> +		 : "=a" (out[CPU_REG_EAX]),
> +		   "=b" (out[CPU_REG_EBX]),
> +		   "=c" (out[CPU_REG_ECX]),
> +		   "=d" (out[CPU_REG_EDX])
>  		 : "a" (leaf), "c" (subleaf));
>  
>  #endif
> @@ -292,8 +292,8 @@ rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
>  		return -EFAULT;
>  
>  	rte_cpu_get_features(feat->leaf & 0xffff0000, 0, regs);
> -	if (((regs[REG_EAX] ^ feat->leaf) & 0xffff0000) ||
> -	      regs[REG_EAX] < feat->leaf)
> +	if (((regs[CPU_REG_EAX] ^ feat->leaf) & 0xffff0000) ||
> +	      regs[CPU_REG_EAX] < feat->leaf)
>  		return 0;
>  
>  	/* get the cpuid leaf containing the desired feature */
> -- 
> 1.9.3
> 

Re: [dpdk-dev] [PATCH 3/3] librte_eal/common: Fix redeclaration of enumerator ‘REG_EAX’

[Qiu, Michael]

On 3/5/2015 9:16 PM, Qiu, Michael wrote:
> include/rte_cpuflags.h:154:2: error: redeclaration of enumerator ‘REG_EAX’
> In file included from /usr/include/signal.h:358:0,
>                  from /usr/include/sys/wait.h:30,
>                  from /root/dpdk/app/test/test_mp_secondary.c:50:
> /usr/include/sys/ucontext.h:180:3: note: previous definition of ‘REG_EAX’ was here
>
> In i686, from REG_EAX to REG_EDX are all defined in
> 	/usr/include/sys/ucontext.h
>
> Rename to CPU_REG_EAX to avoid this issue.
>
> Signed-off-by: Michael Qou <michael.qiu@intel.com>

Sorry, Michael Qou--> Michael Qiu

Thanks,
Michael
> ---
>  .../common/include/arch/x86/rte_cpuflags.h         | 210 ++++++++++-----------
>  1 file changed, 105 insertions(+), 105 deletions(-)
>
> diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
> index a58dd7b..f367b91 100644
> --- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
> +++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
> @@ -151,104 +151,104 @@ enum rte_cpu_flag_t {
>  };
>  
>  enum cpu_register_t {
> -	REG_EAX = 0,
> -	REG_EBX,
> -	REG_ECX,
> -	REG_EDX,
> +	CPU_REG_EAX = 0,
> +	CPU_REG_EBX,
> +	CPU_REG_ECX,
> +	CPU_REG_EDX,
>  };
>  
>  static const struct feature_entry cpu_feature_table[] = {
> -	FEAT_DEF(SSE3, 0x00000001, 0, REG_ECX,  0)
> -	FEAT_DEF(PCLMULQDQ, 0x00000001, 0, REG_ECX,  1)
> -	FEAT_DEF(DTES64, 0x00000001, 0, REG_ECX,  2)
> -	FEAT_DEF(MONITOR, 0x00000001, 0, REG_ECX,  3)
> -	FEAT_DEF(DS_CPL, 0x00000001, 0, REG_ECX,  4)
> -	FEAT_DEF(VMX, 0x00000001, 0, REG_ECX,  5)
> -	FEAT_DEF(SMX, 0x00000001, 0, REG_ECX,  6)
> -	FEAT_DEF(EIST, 0x00000001, 0, REG_ECX,  7)
> -	FEAT_DEF(TM2, 0x00000001, 0, REG_ECX,  8)
> -	FEAT_DEF(SSSE3, 0x00000001, 0, REG_ECX,  9)
> -	FEAT_DEF(CNXT_ID, 0x00000001, 0, REG_ECX, 10)
> -	FEAT_DEF(FMA, 0x00000001, 0, REG_ECX, 12)
> -	FEAT_DEF(CMPXCHG16B, 0x00000001, 0, REG_ECX, 13)
> -	FEAT_DEF(XTPR, 0x00000001, 0, REG_ECX, 14)
> -	FEAT_DEF(PDCM, 0x00000001, 0, REG_ECX, 15)
> -	FEAT_DEF(PCID, 0x00000001, 0, REG_ECX, 17)
> -	FEAT_DEF(DCA, 0x00000001, 0, REG_ECX, 18)
> -	FEAT_DEF(SSE4_1, 0x00000001, 0, REG_ECX, 19)
> -	FEAT_DEF(SSE4_2, 0x00000001, 0, REG_ECX, 20)
> -	FEAT_DEF(X2APIC, 0x00000001, 0, REG_ECX, 21)
> -	FEAT_DEF(MOVBE, 0x00000001, 0, REG_ECX, 22)
> -	FEAT_DEF(POPCNT, 0x00000001, 0, REG_ECX, 23)
> -	FEAT_DEF(TSC_DEADLINE, 0x00000001, 0, REG_ECX, 24)
> -	FEAT_DEF(AES, 0x00000001, 0, REG_ECX, 25)
> -	FEAT_DEF(XSAVE, 0x00000001, 0, REG_ECX, 26)
> -	FEAT_DEF(OSXSAVE, 0x00000001, 0, REG_ECX, 27)
> -	FEAT_DEF(AVX, 0x00000001, 0, REG_ECX, 28)
> -	FEAT_DEF(F16C, 0x00000001, 0, REG_ECX, 29)
> -	FEAT_DEF(RDRAND, 0x00000001, 0, REG_ECX, 30)
> -
> -	FEAT_DEF(FPU, 0x00000001, 0, REG_EDX,  0)
> -	FEAT_DEF(VME, 0x00000001, 0, REG_EDX,  1)
> -	FEAT_DEF(DE, 0x00000001, 0, REG_EDX,  2)
> -	FEAT_DEF(PSE, 0x00000001, 0, REG_EDX,  3)
> -	FEAT_DEF(TSC, 0x00000001, 0, REG_EDX,  4)
> -	FEAT_DEF(MSR, 0x00000001, 0, REG_EDX,  5)
> -	FEAT_DEF(PAE, 0x00000001, 0, REG_EDX,  6)
> -	FEAT_DEF(MCE, 0x00000001, 0, REG_EDX,  7)
> -	FEAT_DEF(CX8, 0x00000001, 0, REG_EDX,  8)
> -	FEAT_DEF(APIC, 0x00000001, 0, REG_EDX,  9)
> -	FEAT_DEF(SEP, 0x00000001, 0, REG_EDX, 11)
> -	FEAT_DEF(MTRR, 0x00000001, 0, REG_EDX, 12)
> -	FEAT_DEF(PGE, 0x00000001, 0, REG_EDX, 13)
> -	FEAT_DEF(MCA, 0x00000001, 0, REG_EDX, 14)
> -	FEAT_DEF(CMOV, 0x00000001, 0, REG_EDX, 15)
> -	FEAT_DEF(PAT, 0x00000001, 0, REG_EDX, 16)
> -	FEAT_DEF(PSE36, 0x00000001, 0, REG_EDX, 17)
> -	FEAT_DEF(PSN, 0x00000001, 0, REG_EDX, 18)
> -	FEAT_DEF(CLFSH, 0x00000001, 0, REG_EDX, 19)
> -	FEAT_DEF(DS, 0x00000001, 0, REG_EDX, 21)
> -	FEAT_DEF(ACPI, 0x00000001, 0, REG_EDX, 22)
> -	FEAT_DEF(MMX, 0x00000001, 0, REG_EDX, 23)
> -	FEAT_DEF(FXSR, 0x00000001, 0, REG_EDX, 24)
> -	FEAT_DEF(SSE, 0x00000001, 0, REG_EDX, 25)
> -	FEAT_DEF(SSE2, 0x00000001, 0, REG_EDX, 26)
> -	FEAT_DEF(SS, 0x00000001, 0, REG_EDX, 27)
> -	FEAT_DEF(HTT, 0x00000001, 0, REG_EDX, 28)
> -	FEAT_DEF(TM, 0x00000001, 0, REG_EDX, 29)
> -	FEAT_DEF(PBE, 0x00000001, 0, REG_EDX, 31)
> -
> -	FEAT_DEF(DIGTEMP, 0x00000006, 0, REG_EAX,  0)
> -	FEAT_DEF(TRBOBST, 0x00000006, 0, REG_EAX,  1)
> -	FEAT_DEF(ARAT, 0x00000006, 0, REG_EAX,  2)
> -	FEAT_DEF(PLN, 0x00000006, 0, REG_EAX,  4)
> -	FEAT_DEF(ECMD, 0x00000006, 0, REG_EAX,  5)
> -	FEAT_DEF(PTM, 0x00000006, 0, REG_EAX,  6)
> -
> -	FEAT_DEF(MPERF_APERF_MSR, 0x00000006, 0, REG_ECX,  0)
> -	FEAT_DEF(ACNT2, 0x00000006, 0, REG_ECX,  1)
> -	FEAT_DEF(ENERGY_EFF, 0x00000006, 0, REG_ECX,  3)
> -
> -	FEAT_DEF(FSGSBASE, 0x00000007, 0, REG_EBX,  0)
> -	FEAT_DEF(BMI1, 0x00000007, 0, REG_EBX,  2)
> -	FEAT_DEF(HLE, 0x00000007, 0, REG_EBX,  4)
> -	FEAT_DEF(AVX2, 0x00000007, 0, REG_EBX,  5)
> -	FEAT_DEF(SMEP, 0x00000007, 0, REG_EBX,  6)
> -	FEAT_DEF(BMI2, 0x00000007, 0, REG_EBX,  7)
> -	FEAT_DEF(ERMS, 0x00000007, 0, REG_EBX,  8)
> -	FEAT_DEF(INVPCID, 0x00000007, 0, REG_EBX, 10)
> -	FEAT_DEF(RTM, 0x00000007, 0, REG_EBX, 11)
> -
> -	FEAT_DEF(LAHF_SAHF, 0x80000001, 0, REG_ECX,  0)
> -	FEAT_DEF(LZCNT, 0x80000001, 0, REG_ECX,  4)
> -
> -	FEAT_DEF(SYSCALL, 0x80000001, 0, REG_EDX, 11)
> -	FEAT_DEF(XD, 0x80000001, 0, REG_EDX, 20)
> -	FEAT_DEF(1GB_PG, 0x80000001, 0, REG_EDX, 26)
> -	FEAT_DEF(RDTSCP, 0x80000001, 0, REG_EDX, 27)
> -	FEAT_DEF(EM64T, 0x80000001, 0, REG_EDX, 29)
> -
> -	FEAT_DEF(INVTSC, 0x80000007, 0, REG_EDX,  8)
> +	FEAT_DEF(SSE3, 0x00000001, 0, CPU_REG_ECX,  0)
> +	FEAT_DEF(PCLMULQDQ, 0x00000001, 0, CPU_REG_ECX,  1)
> +	FEAT_DEF(DTES64, 0x00000001, 0, CPU_REG_ECX,  2)
> +	FEAT_DEF(MONITOR, 0x00000001, 0, CPU_REG_ECX,  3)
> +	FEAT_DEF(DS_CPL, 0x00000001, 0, CPU_REG_ECX,  4)
> +	FEAT_DEF(VMX, 0x00000001, 0, CPU_REG_ECX,  5)
> +	FEAT_DEF(SMX, 0x00000001, 0, CPU_REG_ECX,  6)
> +	FEAT_DEF(EIST, 0x00000001, 0, CPU_REG_ECX,  7)
> +	FEAT_DEF(TM2, 0x00000001, 0, CPU_REG_ECX,  8)
> +	FEAT_DEF(SSSE3, 0x00000001, 0, CPU_REG_ECX,  9)
> +	FEAT_DEF(CNXT_ID, 0x00000001, 0, CPU_REG_ECX, 10)
> +	FEAT_DEF(FMA, 0x00000001, 0, CPU_REG_ECX, 12)
> +	FEAT_DEF(CMPXCHG16B, 0x00000001, 0, CPU_REG_ECX, 13)
> +	FEAT_DEF(XTPR, 0x00000001, 0, CPU_REG_ECX, 14)
> +	FEAT_DEF(PDCM, 0x00000001, 0, CPU_REG_ECX, 15)
> +	FEAT_DEF(PCID, 0x00000001, 0, CPU_REG_ECX, 17)
> +	FEAT_DEF(DCA, 0x00000001, 0, CPU_REG_ECX, 18)
> +	FEAT_DEF(SSE4_1, 0x00000001, 0, CPU_REG_ECX, 19)
> +	FEAT_DEF(SSE4_2, 0x00000001, 0, CPU_REG_ECX, 20)
> +	FEAT_DEF(X2APIC, 0x00000001, 0, CPU_REG_ECX, 21)
> +	FEAT_DEF(MOVBE, 0x00000001, 0, CPU_REG_ECX, 22)
> +	FEAT_DEF(POPCNT, 0x00000001, 0, CPU_REG_ECX, 23)
> +	FEAT_DEF(TSC_DEADLINE, 0x00000001, 0, CPU_REG_ECX, 24)
> +	FEAT_DEF(AES, 0x00000001, 0, CPU_REG_ECX, 25)
> +	FEAT_DEF(XSAVE, 0x00000001, 0, CPU_REG_ECX, 26)
> +	FEAT_DEF(OSXSAVE, 0x00000001, 0, CPU_REG_ECX, 27)
> +	FEAT_DEF(AVX, 0x00000001, 0, CPU_REG_ECX, 28)
> +	FEAT_DEF(F16C, 0x00000001, 0, CPU_REG_ECX, 29)
> +	FEAT_DEF(RDRAND, 0x00000001, 0, CPU_REG_ECX, 30)
> +
> +	FEAT_DEF(FPU, 0x00000001, 0, CPU_REG_EDX,  0)
> +	FEAT_DEF(VME, 0x00000001, 0, CPU_REG_EDX,  1)
> +	FEAT_DEF(DE, 0x00000001, 0, CPU_REG_EDX,  2)
> +	FEAT_DEF(PSE, 0x00000001, 0, CPU_REG_EDX,  3)
> +	FEAT_DEF(TSC, 0x00000001, 0, CPU_REG_EDX,  4)
> +	FEAT_DEF(MSR, 0x00000001, 0, CPU_REG_EDX,  5)
> +	FEAT_DEF(PAE, 0x00000001, 0, CPU_REG_EDX,  6)
> +	FEAT_DEF(MCE, 0x00000001, 0, CPU_REG_EDX,  7)
> +	FEAT_DEF(CX8, 0x00000001, 0, CPU_REG_EDX,  8)
> +	FEAT_DEF(APIC, 0x00000001, 0, CPU_REG_EDX,  9)
> +	FEAT_DEF(SEP, 0x00000001, 0, CPU_REG_EDX, 11)
> +	FEAT_DEF(MTRR, 0x00000001, 0, CPU_REG_EDX, 12)
> +	FEAT_DEF(PGE, 0x00000001, 0, CPU_REG_EDX, 13)
> +	FEAT_DEF(MCA, 0x00000001, 0, CPU_REG_EDX, 14)
> +	FEAT_DEF(CMOV, 0x00000001, 0, CPU_REG_EDX, 15)
> +	FEAT_DEF(PAT, 0x00000001, 0, CPU_REG_EDX, 16)
> +	FEAT_DEF(PSE36, 0x00000001, 0, CPU_REG_EDX, 17)
> +	FEAT_DEF(PSN, 0x00000001, 0, CPU_REG_EDX, 18)
> +	FEAT_DEF(CLFSH, 0x00000001, 0, CPU_REG_EDX, 19)
> +	FEAT_DEF(DS, 0x00000001, 0, CPU_REG_EDX, 21)
> +	FEAT_DEF(ACPI, 0x00000001, 0, CPU_REG_EDX, 22)
> +	FEAT_DEF(MMX, 0x00000001, 0, CPU_REG_EDX, 23)
> +	FEAT_DEF(FXSR, 0x00000001, 0, CPU_REG_EDX, 24)
> +	FEAT_DEF(SSE, 0x00000001, 0, CPU_REG_EDX, 25)
> +	FEAT_DEF(SSE2, 0x00000001, 0, CPU_REG_EDX, 26)
> +	FEAT_DEF(SS, 0x00000001, 0, CPU_REG_EDX, 27)
> +	FEAT_DEF(HTT, 0x00000001, 0, CPU_REG_EDX, 28)
> +	FEAT_DEF(TM, 0x00000001, 0, CPU_REG_EDX, 29)
> +	FEAT_DEF(PBE, 0x00000001, 0, CPU_REG_EDX, 31)
> +
> +	FEAT_DEF(DIGTEMP, 0x00000006, 0, CPU_REG_EAX,  0)
> +	FEAT_DEF(TRBOBST, 0x00000006, 0, CPU_REG_EAX,  1)
> +	FEAT_DEF(ARAT, 0x00000006, 0, CPU_REG_EAX,  2)
> +	FEAT_DEF(PLN, 0x00000006, 0, CPU_REG_EAX,  4)
> +	FEAT_DEF(ECMD, 0x00000006, 0, CPU_REG_EAX,  5)
> +	FEAT_DEF(PTM, 0x00000006, 0, CPU_REG_EAX,  6)
> +
> +	FEAT_DEF(MPERF_APERF_MSR, 0x00000006, 0, CPU_REG_ECX,  0)
> +	FEAT_DEF(ACNT2, 0x00000006, 0, CPU_REG_ECX,  1)
> +	FEAT_DEF(ENERGY_EFF, 0x00000006, 0, CPU_REG_ECX,  3)
> +
> +	FEAT_DEF(FSGSBASE, 0x00000007, 0, CPU_REG_EBX,  0)
> +	FEAT_DEF(BMI1, 0x00000007, 0, CPU_REG_EBX,  2)
> +	FEAT_DEF(HLE, 0x00000007, 0, CPU_REG_EBX,  4)
> +	FEAT_DEF(AVX2, 0x00000007, 0, CPU_REG_EBX,  5)
> +	FEAT_DEF(SMEP, 0x00000007, 0, CPU_REG_EBX,  6)
> +	FEAT_DEF(BMI2, 0x00000007, 0, CPU_REG_EBX,  7)
> +	FEAT_DEF(ERMS, 0x00000007, 0, CPU_REG_EBX,  8)
> +	FEAT_DEF(INVPCID, 0x00000007, 0, CPU_REG_EBX, 10)
> +	FEAT_DEF(RTM, 0x00000007, 0, CPU_REG_EBX, 11)
> +
> +	FEAT_DEF(LAHF_SAHF, 0x80000001, 0, CPU_REG_ECX,  0)
> +	FEAT_DEF(LZCNT, 0x80000001, 0, CPU_REG_ECX,  4)
> +
> +	FEAT_DEF(SYSCALL, 0x80000001, 0, CPU_REG_EDX, 11)
> +	FEAT_DEF(XD, 0x80000001, 0, CPU_REG_EDX, 20)
> +	FEAT_DEF(1GB_PG, 0x80000001, 0, CPU_REG_EDX, 26)
> +	FEAT_DEF(RDTSCP, 0x80000001, 0, CPU_REG_EDX, 27)
> +	FEAT_DEF(EM64T, 0x80000001, 0, CPU_REG_EDX, 29)
> +
> +	FEAT_DEF(INVTSC, 0x80000007, 0, CPU_REG_EDX,  8)
>  };
>  
>  static inline void
> @@ -257,18 +257,18 @@ rte_cpu_get_features(uint32_t leaf, uint32_t subleaf, cpuid_registers_t out)
>  #if defined(__i386__) && defined(__PIC__)
>      /* %ebx is a forbidden register if we compile with -fPIC or -fPIE */
>      asm volatile("movl %%ebx,%0 ; cpuid ; xchgl %%ebx,%0"
> -		 : "=r" (out[REG_EBX]),
> -		   "=a" (out[REG_EAX]),
> -		   "=c" (out[REG_ECX]),
> -		   "=d" (out[REG_EDX])
> +		 : "=r" (out[CPU_REG_EBX]),
> +		   "=a" (out[CPU_REG_EAX]),
> +		   "=c" (out[CPU_REG_ECX]),
> +		   "=d" (out[CPU_REG_EDX])
>  		 : "a" (leaf), "c" (subleaf));
>  #else
>  
>      asm volatile("cpuid"
> -		 : "=a" (out[REG_EAX]),
> -		   "=b" (out[REG_EBX]),
> -		   "=c" (out[REG_ECX]),
> -		   "=d" (out[REG_EDX])
> +		 : "=a" (out[CPU_REG_EAX]),
> +		   "=b" (out[CPU_REG_EBX]),
> +		   "=c" (out[CPU_REG_ECX]),
> +		   "=d" (out[CPU_REG_EDX])
>  		 : "a" (leaf), "c" (subleaf));
>  
>  #endif
> @@ -292,8 +292,8 @@ rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
>  		return -EFAULT;
>  
>  	rte_cpu_get_features(feat->leaf & 0xffff0000, 0, regs);
> -	if (((regs[REG_EAX] ^ feat->leaf) & 0xffff0000) ||
> -	      regs[REG_EAX] < feat->leaf)
> +	if (((regs[CPU_REG_EAX] ^ feat->leaf) & 0xffff0000) ||
> +	      regs[CPU_REG_EAX] < feat->leaf)
>  		return 0;
>  
>  	/* get the cpuid leaf containing the desired feature */

Re: [dpdk-dev] [PATCH 3/3] librte_eal/common: Fix redeclaration of enumerator ‘REG_EAX’

[David Marchand]

On Thu, Mar 5, 2015 at 2:23 PM, Bruce Richardson <bruce.richardson@intel.com
> wrote:

> On Thu, Mar 05, 2015 at 09:15:39PM +0800, Michael Qiu wrote:
> > include/rte_cpuflags.h:154:2: error: redeclaration of enumerator
> ‘REG_EAX’
> > In file included from /usr/include/signal.h:358:0,
> >                  from /usr/include/sys/wait.h:30,
> >                  from /root/dpdk/app/test/test_mp_secondary.c:50:
> > /usr/include/sys/ucontext.h:180:3: note: previous definition of
> ‘REG_EAX’ was here
> >
> > In i686, from REG_EAX to REG_EDX are all defined in
> >       /usr/include/sys/ucontext.h
>

Well, this is the same for x86_64.

$ grep -rl '\<REG_EAX\>' /usr/include/
/usr/include/x86_64-linux-gnu/sys/ucontext.h

$ ls -l /usr/include/sys/ucontext.h
lrwxrwxrwx 1 root root 34 Feb 22 12:45 /usr/include/sys/ucontext.h ->
../x86_64-linux-gnu/sys/ucontext.h

So I am not sure I understand why we redefine stuff already available from
the toolchain.
Rather than prefixing, I think we should get rid of this and include the
right header.


-- 
David Marchand

Re: [dpdk-dev] [PATCH 3/3] librte_eal/common: Fix redeclaration of enumerator ‘REG_EAX’

[Qiu, Michael]

On 3/5/2015 9:24 PM, Richardson, Bruce wrote:
> On Thu, Mar 05, 2015 at 09:15:39PM +0800, Michael Qiu wrote:
>> include/rte_cpuflags.h:154:2: error: redeclaration of enumerator ‘REG_EAX’
>> In file included from /usr/include/signal.h:358:0,
>>                  from /usr/include/sys/wait.h:30,
>>                  from /root/dpdk/app/test/test_mp_secondary.c:50:
>> /usr/include/sys/ucontext.h:180:3: note: previous definition of ‘REG_EAX’ was here
>>
>> In i686, from REG_EAX to REG_EDX are all defined in
>> 	/usr/include/sys/ucontext.h
>>
>> Rename to CPU_REG_EAX to avoid this issue.
> RTE_ prefix for consistency with other public DPDK symbols perhaps?

Hi, Bruce

Yes, agree.

I will send out v2 now.

Thanks,
Michael
> /Bruce
>
>> Signed-off-by: Michael Qou <michael.qiu@intel.com>
>> ---
>>  .../common/include/arch/x86/rte_cpuflags.h         | 210 ++++++++++-----------
>>  1 file changed, 105 insertions(+), 105 deletions(-)
>>
>> diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
>> index a58dd7b..f367b91 100644
>> --- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
>> +++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
>> @@ -151,104 +151,104 @@ enum rte_cpu_flag_t {
>>  };
>>  
>>  enum cpu_register_t {
>> -	REG_EAX = 0,
>> -	REG_EBX,
>> -	REG_ECX,
>> -	REG_EDX,
>> +	CPU_REG_EAX = 0,
>> +	CPU_REG_EBX,
>> +	CPU_REG_ECX,
>> +	CPU_REG_EDX,
>>  };
>>  
>>  static const struct feature_entry cpu_feature_table[] = {
>> -	FEAT_DEF(SSE3, 0x00000001, 0, REG_ECX,  0)
>> -	FEAT_DEF(PCLMULQDQ, 0x00000001, 0, REG_ECX,  1)
>> -	FEAT_DEF(DTES64, 0x00000001, 0, REG_ECX,  2)
>> -	FEAT_DEF(MONITOR, 0x00000001, 0, REG_ECX,  3)
>> -	FEAT_DEF(DS_CPL, 0x00000001, 0, REG_ECX,  4)
>> -	FEAT_DEF(VMX, 0x00000001, 0, REG_ECX,  5)
>> -	FEAT_DEF(SMX, 0x00000001, 0, REG_ECX,  6)
>> -	FEAT_DEF(EIST, 0x00000001, 0, REG_ECX,  7)
>> -	FEAT_DEF(TM2, 0x00000001, 0, REG_ECX,  8)
>> -	FEAT_DEF(SSSE3, 0x00000001, 0, REG_ECX,  9)
>> -	FEAT_DEF(CNXT_ID, 0x00000001, 0, REG_ECX, 10)
>> -	FEAT_DEF(FMA, 0x00000001, 0, REG_ECX, 12)
>> -	FEAT_DEF(CMPXCHG16B, 0x00000001, 0, REG_ECX, 13)
>> -	FEAT_DEF(XTPR, 0x00000001, 0, REG_ECX, 14)
>> -	FEAT_DEF(PDCM, 0x00000001, 0, REG_ECX, 15)
>> -	FEAT_DEF(PCID, 0x00000001, 0, REG_ECX, 17)
>> -	FEAT_DEF(DCA, 0x00000001, 0, REG_ECX, 18)
>> -	FEAT_DEF(SSE4_1, 0x00000001, 0, REG_ECX, 19)
>> -	FEAT_DEF(SSE4_2, 0x00000001, 0, REG_ECX, 20)
>> -	FEAT_DEF(X2APIC, 0x00000001, 0, REG_ECX, 21)
>> -	FEAT_DEF(MOVBE, 0x00000001, 0, REG_ECX, 22)
>> -	FEAT_DEF(POPCNT, 0x00000001, 0, REG_ECX, 23)
>> -	FEAT_DEF(TSC_DEADLINE, 0x00000001, 0, REG_ECX, 24)
>> -	FEAT_DEF(AES, 0x00000001, 0, REG_ECX, 25)
>> -	FEAT_DEF(XSAVE, 0x00000001, 0, REG_ECX, 26)
>> -	FEAT_DEF(OSXSAVE, 0x00000001, 0, REG_ECX, 27)
>> -	FEAT_DEF(AVX, 0x00000001, 0, REG_ECX, 28)
>> -	FEAT_DEF(F16C, 0x00000001, 0, REG_ECX, 29)
>> -	FEAT_DEF(RDRAND, 0x00000001, 0, REG_ECX, 30)
>> -
>> -	FEAT_DEF(FPU, 0x00000001, 0, REG_EDX,  0)
>> -	FEAT_DEF(VME, 0x00000001, 0, REG_EDX,  1)
>> -	FEAT_DEF(DE, 0x00000001, 0, REG_EDX,  2)
>> -	FEAT_DEF(PSE, 0x00000001, 0, REG_EDX,  3)
>> -	FEAT_DEF(TSC, 0x00000001, 0, REG_EDX,  4)
>> -	FEAT_DEF(MSR, 0x00000001, 0, REG_EDX,  5)
>> -	FEAT_DEF(PAE, 0x00000001, 0, REG_EDX,  6)
>> -	FEAT_DEF(MCE, 0x00000001, 0, REG_EDX,  7)
>> -	FEAT_DEF(CX8, 0x00000001, 0, REG_EDX,  8)
>> -	FEAT_DEF(APIC, 0x00000001, 0, REG_EDX,  9)
>> -	FEAT_DEF(SEP, 0x00000001, 0, REG_EDX, 11)
>> -	FEAT_DEF(MTRR, 0x00000001, 0, REG_EDX, 12)
>> -	FEAT_DEF(PGE, 0x00000001, 0, REG_EDX, 13)
>> -	FEAT_DEF(MCA, 0x00000001, 0, REG_EDX, 14)
>> -	FEAT_DEF(CMOV, 0x00000001, 0, REG_EDX, 15)
>> -	FEAT_DEF(PAT, 0x00000001, 0, REG_EDX, 16)
>> -	FEAT_DEF(PSE36, 0x00000001, 0, REG_EDX, 17)
>> -	FEAT_DEF(PSN, 0x00000001, 0, REG_EDX, 18)
>> -	FEAT_DEF(CLFSH, 0x00000001, 0, REG_EDX, 19)
>> -	FEAT_DEF(DS, 0x00000001, 0, REG_EDX, 21)
>> -	FEAT_DEF(ACPI, 0x00000001, 0, REG_EDX, 22)
>> -	FEAT_DEF(MMX, 0x00000001, 0, REG_EDX, 23)
>> -	FEAT_DEF(FXSR, 0x00000001, 0, REG_EDX, 24)
>> -	FEAT_DEF(SSE, 0x00000001, 0, REG_EDX, 25)
>> -	FEAT_DEF(SSE2, 0x00000001, 0, REG_EDX, 26)
>> -	FEAT_DEF(SS, 0x00000001, 0, REG_EDX, 27)
>> -	FEAT_DEF(HTT, 0x00000001, 0, REG_EDX, 28)
>> -	FEAT_DEF(TM, 0x00000001, 0, REG_EDX, 29)
>> -	FEAT_DEF(PBE, 0x00000001, 0, REG_EDX, 31)
>> -
>> -	FEAT_DEF(DIGTEMP, 0x00000006, 0, REG_EAX,  0)
>> -	FEAT_DEF(TRBOBST, 0x00000006, 0, REG_EAX,  1)
>> -	FEAT_DEF(ARAT, 0x00000006, 0, REG_EAX,  2)
>> -	FEAT_DEF(PLN, 0x00000006, 0, REG_EAX,  4)
>> -	FEAT_DEF(ECMD, 0x00000006, 0, REG_EAX,  5)
>> -	FEAT_DEF(PTM, 0x00000006, 0, REG_EAX,  6)
>> -
>> -	FEAT_DEF(MPERF_APERF_MSR, 0x00000006, 0, REG_ECX,  0)
>> -	FEAT_DEF(ACNT2, 0x00000006, 0, REG_ECX,  1)
>> -	FEAT_DEF(ENERGY_EFF, 0x00000006, 0, REG_ECX,  3)
>> -
>> -	FEAT_DEF(FSGSBASE, 0x00000007, 0, REG_EBX,  0)
>> -	FEAT_DEF(BMI1, 0x00000007, 0, REG_EBX,  2)
>> -	FEAT_DEF(HLE, 0x00000007, 0, REG_EBX,  4)
>> -	FEAT_DEF(AVX2, 0x00000007, 0, REG_EBX,  5)
>> -	FEAT_DEF(SMEP, 0x00000007, 0, REG_EBX,  6)
>> -	FEAT_DEF(BMI2, 0x00000007, 0, REG_EBX,  7)
>> -	FEAT_DEF(ERMS, 0x00000007, 0, REG_EBX,  8)
>> -	FEAT_DEF(INVPCID, 0x00000007, 0, REG_EBX, 10)
>> -	FEAT_DEF(RTM, 0x00000007, 0, REG_EBX, 11)
>> -
>> -	FEAT_DEF(LAHF_SAHF, 0x80000001, 0, REG_ECX,  0)
>> -	FEAT_DEF(LZCNT, 0x80000001, 0, REG_ECX,  4)
>> -
>> -	FEAT_DEF(SYSCALL, 0x80000001, 0, REG_EDX, 11)
>> -	FEAT_DEF(XD, 0x80000001, 0, REG_EDX, 20)
>> -	FEAT_DEF(1GB_PG, 0x80000001, 0, REG_EDX, 26)
>> -	FEAT_DEF(RDTSCP, 0x80000001, 0, REG_EDX, 27)
>> -	FEAT_DEF(EM64T, 0x80000001, 0, REG_EDX, 29)
>> -
>> -	FEAT_DEF(INVTSC, 0x80000007, 0, REG_EDX,  8)
>> +	FEAT_DEF(SSE3, 0x00000001, 0, CPU_REG_ECX,  0)
>> +	FEAT_DEF(PCLMULQDQ, 0x00000001, 0, CPU_REG_ECX,  1)
>> +	FEAT_DEF(DTES64, 0x00000001, 0, CPU_REG_ECX,  2)
>> +	FEAT_DEF(MONITOR, 0x00000001, 0, CPU_REG_ECX,  3)
>> +	FEAT_DEF(DS_CPL, 0x00000001, 0, CPU_REG_ECX,  4)
>> +	FEAT_DEF(VMX, 0x00000001, 0, CPU_REG_ECX,  5)
>> +	FEAT_DEF(SMX, 0x00000001, 0, CPU_REG_ECX,  6)
>> +	FEAT_DEF(EIST, 0x00000001, 0, CPU_REG_ECX,  7)
>> +	FEAT_DEF(TM2, 0x00000001, 0, CPU_REG_ECX,  8)
>> +	FEAT_DEF(SSSE3, 0x00000001, 0, CPU_REG_ECX,  9)
>> +	FEAT_DEF(CNXT_ID, 0x00000001, 0, CPU_REG_ECX, 10)
>> +	FEAT_DEF(FMA, 0x00000001, 0, CPU_REG_ECX, 12)
>> +	FEAT_DEF(CMPXCHG16B, 0x00000001, 0, CPU_REG_ECX, 13)
>> +	FEAT_DEF(XTPR, 0x00000001, 0, CPU_REG_ECX, 14)
>> +	FEAT_DEF(PDCM, 0x00000001, 0, CPU_REG_ECX, 15)
>> +	FEAT_DEF(PCID, 0x00000001, 0, CPU_REG_ECX, 17)
>> +	FEAT_DEF(DCA, 0x00000001, 0, CPU_REG_ECX, 18)
>> +	FEAT_DEF(SSE4_1, 0x00000001, 0, CPU_REG_ECX, 19)
>> +	FEAT_DEF(SSE4_2, 0x00000001, 0, CPU_REG_ECX, 20)
>> +	FEAT_DEF(X2APIC, 0x00000001, 0, CPU_REG_ECX, 21)
>> +	FEAT_DEF(MOVBE, 0x00000001, 0, CPU_REG_ECX, 22)
>> +	FEAT_DEF(POPCNT, 0x00000001, 0, CPU_REG_ECX, 23)
>> +	FEAT_DEF(TSC_DEADLINE, 0x00000001, 0, CPU_REG_ECX, 24)
>> +	FEAT_DEF(AES, 0x00000001, 0, CPU_REG_ECX, 25)
>> +	FEAT_DEF(XSAVE, 0x00000001, 0, CPU_REG_ECX, 26)
>> +	FEAT_DEF(OSXSAVE, 0x00000001, 0, CPU_REG_ECX, 27)
>> +	FEAT_DEF(AVX, 0x00000001, 0, CPU_REG_ECX, 28)
>> +	FEAT_DEF(F16C, 0x00000001, 0, CPU_REG_ECX, 29)
>> +	FEAT_DEF(RDRAND, 0x00000001, 0, CPU_REG_ECX, 30)
>> +
>> +	FEAT_DEF(FPU, 0x00000001, 0, CPU_REG_EDX,  0)
>> +	FEAT_DEF(VME, 0x00000001, 0, CPU_REG_EDX,  1)
>> +	FEAT_DEF(DE, 0x00000001, 0, CPU_REG_EDX,  2)
>> +	FEAT_DEF(PSE, 0x00000001, 0, CPU_REG_EDX,  3)
>> +	FEAT_DEF(TSC, 0x00000001, 0, CPU_REG_EDX,  4)
>> +	FEAT_DEF(MSR, 0x00000001, 0, CPU_REG_EDX,  5)
>> +	FEAT_DEF(PAE, 0x00000001, 0, CPU_REG_EDX,  6)
>> +	FEAT_DEF(MCE, 0x00000001, 0, CPU_REG_EDX,  7)
>> +	FEAT_DEF(CX8, 0x00000001, 0, CPU_REG_EDX,  8)
>> +	FEAT_DEF(APIC, 0x00000001, 0, CPU_REG_EDX,  9)
>> +	FEAT_DEF(SEP, 0x00000001, 0, CPU_REG_EDX, 11)
>> +	FEAT_DEF(MTRR, 0x00000001, 0, CPU_REG_EDX, 12)
>> +	FEAT_DEF(PGE, 0x00000001, 0, CPU_REG_EDX, 13)
>> +	FEAT_DEF(MCA, 0x00000001, 0, CPU_REG_EDX, 14)
>> +	FEAT_DEF(CMOV, 0x00000001, 0, CPU_REG_EDX, 15)
>> +	FEAT_DEF(PAT, 0x00000001, 0, CPU_REG_EDX, 16)
>> +	FEAT_DEF(PSE36, 0x00000001, 0, CPU_REG_EDX, 17)
>> +	FEAT_DEF(PSN, 0x00000001, 0, CPU_REG_EDX, 18)
>> +	FEAT_DEF(CLFSH, 0x00000001, 0, CPU_REG_EDX, 19)
>> +	FEAT_DEF(DS, 0x00000001, 0, CPU_REG_EDX, 21)
>> +	FEAT_DEF(ACPI, 0x00000001, 0, CPU_REG_EDX, 22)
>> +	FEAT_DEF(MMX, 0x00000001, 0, CPU_REG_EDX, 23)
>> +	FEAT_DEF(FXSR, 0x00000001, 0, CPU_REG_EDX, 24)
>> +	FEAT_DEF(SSE, 0x00000001, 0, CPU_REG_EDX, 25)
>> +	FEAT_DEF(SSE2, 0x00000001, 0, CPU_REG_EDX, 26)
>> +	FEAT_DEF(SS, 0x00000001, 0, CPU_REG_EDX, 27)
>> +	FEAT_DEF(HTT, 0x00000001, 0, CPU_REG_EDX, 28)
>> +	FEAT_DEF(TM, 0x00000001, 0, CPU_REG_EDX, 29)
>> +	FEAT_DEF(PBE, 0x00000001, 0, CPU_REG_EDX, 31)
>> +
>> +	FEAT_DEF(DIGTEMP, 0x00000006, 0, CPU_REG_EAX,  0)
>> +	FEAT_DEF(TRBOBST, 0x00000006, 0, CPU_REG_EAX,  1)
>> +	FEAT_DEF(ARAT, 0x00000006, 0, CPU_REG_EAX,  2)
>> +	FEAT_DEF(PLN, 0x00000006, 0, CPU_REG_EAX,  4)
>> +	FEAT_DEF(ECMD, 0x00000006, 0, CPU_REG_EAX,  5)
>> +	FEAT_DEF(PTM, 0x00000006, 0, CPU_REG_EAX,  6)
>> +
>> +	FEAT_DEF(MPERF_APERF_MSR, 0x00000006, 0, CPU_REG_ECX,  0)
>> +	FEAT_DEF(ACNT2, 0x00000006, 0, CPU_REG_ECX,  1)
>> +	FEAT_DEF(ENERGY_EFF, 0x00000006, 0, CPU_REG_ECX,  3)
>> +
>> +	FEAT_DEF(FSGSBASE, 0x00000007, 0, CPU_REG_EBX,  0)
>> +	FEAT_DEF(BMI1, 0x00000007, 0, CPU_REG_EBX,  2)
>> +	FEAT_DEF(HLE, 0x00000007, 0, CPU_REG_EBX,  4)
>> +	FEAT_DEF(AVX2, 0x00000007, 0, CPU_REG_EBX,  5)
>> +	FEAT_DEF(SMEP, 0x00000007, 0, CPU_REG_EBX,  6)
>> +	FEAT_DEF(BMI2, 0x00000007, 0, CPU_REG_EBX,  7)
>> +	FEAT_DEF(ERMS, 0x00000007, 0, CPU_REG_EBX,  8)
>> +	FEAT_DEF(INVPCID, 0x00000007, 0, CPU_REG_EBX, 10)
>> +	FEAT_DEF(RTM, 0x00000007, 0, CPU_REG_EBX, 11)
>> +
>> +	FEAT_DEF(LAHF_SAHF, 0x80000001, 0, CPU_REG_ECX,  0)
>> +	FEAT_DEF(LZCNT, 0x80000001, 0, CPU_REG_ECX,  4)
>> +
>> +	FEAT_DEF(SYSCALL, 0x80000001, 0, CPU_REG_EDX, 11)
>> +	FEAT_DEF(XD, 0x80000001, 0, CPU_REG_EDX, 20)
>> +	FEAT_DEF(1GB_PG, 0x80000001, 0, CPU_REG_EDX, 26)
>> +	FEAT_DEF(RDTSCP, 0x80000001, 0, CPU_REG_EDX, 27)
>> +	FEAT_DEF(EM64T, 0x80000001, 0, CPU_REG_EDX, 29)
>> +
>> +	FEAT_DEF(INVTSC, 0x80000007, 0, CPU_REG_EDX,  8)
>>  };
>>  
>>  static inline void
>> @@ -257,18 +257,18 @@ rte_cpu_get_features(uint32_t leaf, uint32_t subleaf, cpuid_registers_t out)
>>  #if defined(__i386__) && defined(__PIC__)
>>      /* %ebx is a forbidden register if we compile with -fPIC or -fPIE */
>>      asm volatile("movl %%ebx,%0 ; cpuid ; xchgl %%ebx,%0"
>> -		 : "=r" (out[REG_EBX]),
>> -		   "=a" (out[REG_EAX]),
>> -		   "=c" (out[REG_ECX]),
>> -		   "=d" (out[REG_EDX])
>> +		 : "=r" (out[CPU_REG_EBX]),
>> +		   "=a" (out[CPU_REG_EAX]),
>> +		   "=c" (out[CPU_REG_ECX]),
>> +		   "=d" (out[CPU_REG_EDX])
>>  		 : "a" (leaf), "c" (subleaf));
>>  #else
>>  
>>      asm volatile("cpuid"
>> -		 : "=a" (out[REG_EAX]),
>> -		   "=b" (out[REG_EBX]),
>> -		   "=c" (out[REG_ECX]),
>> -		   "=d" (out[REG_EDX])
>> +		 : "=a" (out[CPU_REG_EAX]),
>> +		   "=b" (out[CPU_REG_EBX]),
>> +		   "=c" (out[CPU_REG_ECX]),
>> +		   "=d" (out[CPU_REG_EDX])
>>  		 : "a" (leaf), "c" (subleaf));
>>  
>>  #endif
>> @@ -292,8 +292,8 @@ rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
>>  		return -EFAULT;
>>  
>>  	rte_cpu_get_features(feat->leaf & 0xffff0000, 0, regs);
>> -	if (((regs[REG_EAX] ^ feat->leaf) & 0xffff0000) ||
>> -	      regs[REG_EAX] < feat->leaf)
>> +	if (((regs[CPU_REG_EAX] ^ feat->leaf) & 0xffff0000) ||
>> +	      regs[CPU_REG_EAX] < feat->leaf)
>>  		return 0;
>>  
>>  	/* get the cpuid leaf containing the desired feature */
>> -- 
>> 1.9.3
>>

[dpdk-dev] [PATCH 3/3 v2] =?UTF-8?q?librte=5Feal/common:=20Fix=20redeclaration=20of?= =?UTF-8?q?=20enumerator=20=E2=80=98REG=5FEAX=E2=80=99?=

[Michael Qiu]

include/rte_cpuflags.h:154:2: error: redeclaration of enumerator ‘REG_EAX’
In file included from /usr/include/signal.h:358:0,
                 from /usr/include/sys/wait.h:30,
                 from /root/dpdk/app/test/test_mp_secondary.c:50:
/usr/include/sys/ucontext.h:180:3: note: previous definition of ‘REG_EAX’ was here

In i686, from REG_EAX to REG_EDX are all defined in
	/usr/include/sys/ucontext.h

Rename to CPU_REG_EAX to avoid this issue.

Signed-off-by: Michael Qou <michael.qiu@intel.com>
---
v2 --> v1:
	rename CPU_REG_EAX to RTE_REG_EAX

 .../common/include/arch/x86/rte_cpuflags.h         | 210 ++++++++++-----------
 1 file changed, 105 insertions(+), 105 deletions(-)

diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
index a58dd7b..dd56553 100644
--- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
+++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
@@ -151,104 +151,104 @@ enum rte_cpu_flag_t {
 };
 
 enum cpu_register_t {
-	REG_EAX = 0,
-	REG_EBX,
-	REG_ECX,
-	REG_EDX,
+	RTE_REG_EAX = 0,
+	RTE_REG_EBX,
+	RTE_REG_ECX,
+	RTE_REG_EDX,
 };
 
 static const struct feature_entry cpu_feature_table[] = {
-	FEAT_DEF(SSE3, 0x00000001, 0, REG_ECX,  0)
-	FEAT_DEF(PCLMULQDQ, 0x00000001, 0, REG_ECX,  1)
-	FEAT_DEF(DTES64, 0x00000001, 0, REG_ECX,  2)
-	FEAT_DEF(MONITOR, 0x00000001, 0, REG_ECX,  3)
-	FEAT_DEF(DS_CPL, 0x00000001, 0, REG_ECX,  4)
-	FEAT_DEF(VMX, 0x00000001, 0, REG_ECX,  5)
-	FEAT_DEF(SMX, 0x00000001, 0, REG_ECX,  6)
-	FEAT_DEF(EIST, 0x00000001, 0, REG_ECX,  7)
-	FEAT_DEF(TM2, 0x00000001, 0, REG_ECX,  8)
-	FEAT_DEF(SSSE3, 0x00000001, 0, REG_ECX,  9)
-	FEAT_DEF(CNXT_ID, 0x00000001, 0, REG_ECX, 10)
-	FEAT_DEF(FMA, 0x00000001, 0, REG_ECX, 12)
-	FEAT_DEF(CMPXCHG16B, 0x00000001, 0, REG_ECX, 13)
-	FEAT_DEF(XTPR, 0x00000001, 0, REG_ECX, 14)
-	FEAT_DEF(PDCM, 0x00000001, 0, REG_ECX, 15)
-	FEAT_DEF(PCID, 0x00000001, 0, REG_ECX, 17)
-	FEAT_DEF(DCA, 0x00000001, 0, REG_ECX, 18)
-	FEAT_DEF(SSE4_1, 0x00000001, 0, REG_ECX, 19)
-	FEAT_DEF(SSE4_2, 0x00000001, 0, REG_ECX, 20)
-	FEAT_DEF(X2APIC, 0x00000001, 0, REG_ECX, 21)
-	FEAT_DEF(MOVBE, 0x00000001, 0, REG_ECX, 22)
-	FEAT_DEF(POPCNT, 0x00000001, 0, REG_ECX, 23)
-	FEAT_DEF(TSC_DEADLINE, 0x00000001, 0, REG_ECX, 24)
-	FEAT_DEF(AES, 0x00000001, 0, REG_ECX, 25)
-	FEAT_DEF(XSAVE, 0x00000001, 0, REG_ECX, 26)
-	FEAT_DEF(OSXSAVE, 0x00000001, 0, REG_ECX, 27)
-	FEAT_DEF(AVX, 0x00000001, 0, REG_ECX, 28)
-	FEAT_DEF(F16C, 0x00000001, 0, REG_ECX, 29)
-	FEAT_DEF(RDRAND, 0x00000001, 0, REG_ECX, 30)
-
-	FEAT_DEF(FPU, 0x00000001, 0, REG_EDX,  0)
-	FEAT_DEF(VME, 0x00000001, 0, REG_EDX,  1)
-	FEAT_DEF(DE, 0x00000001, 0, REG_EDX,  2)
-	FEAT_DEF(PSE, 0x00000001, 0, REG_EDX,  3)
-	FEAT_DEF(TSC, 0x00000001, 0, REG_EDX,  4)
-	FEAT_DEF(MSR, 0x00000001, 0, REG_EDX,  5)
-	FEAT_DEF(PAE, 0x00000001, 0, REG_EDX,  6)
-	FEAT_DEF(MCE, 0x00000001, 0, REG_EDX,  7)
-	FEAT_DEF(CX8, 0x00000001, 0, REG_EDX,  8)
-	FEAT_DEF(APIC, 0x00000001, 0, REG_EDX,  9)
-	FEAT_DEF(SEP, 0x00000001, 0, REG_EDX, 11)
-	FEAT_DEF(MTRR, 0x00000001, 0, REG_EDX, 12)
-	FEAT_DEF(PGE, 0x00000001, 0, REG_EDX, 13)
-	FEAT_DEF(MCA, 0x00000001, 0, REG_EDX, 14)
-	FEAT_DEF(CMOV, 0x00000001, 0, REG_EDX, 15)
-	FEAT_DEF(PAT, 0x00000001, 0, REG_EDX, 16)
-	FEAT_DEF(PSE36, 0x00000001, 0, REG_EDX, 17)
-	FEAT_DEF(PSN, 0x00000001, 0, REG_EDX, 18)
-	FEAT_DEF(CLFSH, 0x00000001, 0, REG_EDX, 19)
-	FEAT_DEF(DS, 0x00000001, 0, REG_EDX, 21)
-	FEAT_DEF(ACPI, 0x00000001, 0, REG_EDX, 22)
-	FEAT_DEF(MMX, 0x00000001, 0, REG_EDX, 23)
-	FEAT_DEF(FXSR, 0x00000001, 0, REG_EDX, 24)
-	FEAT_DEF(SSE, 0x00000001, 0, REG_EDX, 25)
-	FEAT_DEF(SSE2, 0x00000001, 0, REG_EDX, 26)
-	FEAT_DEF(SS, 0x00000001, 0, REG_EDX, 27)
-	FEAT_DEF(HTT, 0x00000001, 0, REG_EDX, 28)
-	FEAT_DEF(TM, 0x00000001, 0, REG_EDX, 29)
-	FEAT_DEF(PBE, 0x00000001, 0, REG_EDX, 31)
-
-	FEAT_DEF(DIGTEMP, 0x00000006, 0, REG_EAX,  0)
-	FEAT_DEF(TRBOBST, 0x00000006, 0, REG_EAX,  1)
-	FEAT_DEF(ARAT, 0x00000006, 0, REG_EAX,  2)
-	FEAT_DEF(PLN, 0x00000006, 0, REG_EAX,  4)
-	FEAT_DEF(ECMD, 0x00000006, 0, REG_EAX,  5)
-	FEAT_DEF(PTM, 0x00000006, 0, REG_EAX,  6)
-
-	FEAT_DEF(MPERF_APERF_MSR, 0x00000006, 0, REG_ECX,  0)
-	FEAT_DEF(ACNT2, 0x00000006, 0, REG_ECX,  1)
-	FEAT_DEF(ENERGY_EFF, 0x00000006, 0, REG_ECX,  3)
-
-	FEAT_DEF(FSGSBASE, 0x00000007, 0, REG_EBX,  0)
-	FEAT_DEF(BMI1, 0x00000007, 0, REG_EBX,  2)
-	FEAT_DEF(HLE, 0x00000007, 0, REG_EBX,  4)
-	FEAT_DEF(AVX2, 0x00000007, 0, REG_EBX,  5)
-	FEAT_DEF(SMEP, 0x00000007, 0, REG_EBX,  6)
-	FEAT_DEF(BMI2, 0x00000007, 0, REG_EBX,  7)
-	FEAT_DEF(ERMS, 0x00000007, 0, REG_EBX,  8)
-	FEAT_DEF(INVPCID, 0x00000007, 0, REG_EBX, 10)
-	FEAT_DEF(RTM, 0x00000007, 0, REG_EBX, 11)
-
-	FEAT_DEF(LAHF_SAHF, 0x80000001, 0, REG_ECX,  0)
-	FEAT_DEF(LZCNT, 0x80000001, 0, REG_ECX,  4)
-
-	FEAT_DEF(SYSCALL, 0x80000001, 0, REG_EDX, 11)
-	FEAT_DEF(XD, 0x80000001, 0, REG_EDX, 20)
-	FEAT_DEF(1GB_PG, 0x80000001, 0, REG_EDX, 26)
-	FEAT_DEF(RDTSCP, 0x80000001, 0, REG_EDX, 27)
-	FEAT_DEF(EM64T, 0x80000001, 0, REG_EDX, 29)
-
-	FEAT_DEF(INVTSC, 0x80000007, 0, REG_EDX,  8)
+	FEAT_DEF(SSE3, 0x00000001, 0, RTE_REG_ECX,  0)
+	FEAT_DEF(PCLMULQDQ, 0x00000001, 0, RTE_REG_ECX,  1)
+	FEAT_DEF(DTES64, 0x00000001, 0, RTE_REG_ECX,  2)
+	FEAT_DEF(MONITOR, 0x00000001, 0, RTE_REG_ECX,  3)
+	FEAT_DEF(DS_CPL, 0x00000001, 0, RTE_REG_ECX,  4)
+	FEAT_DEF(VMX, 0x00000001, 0, RTE_REG_ECX,  5)
+	FEAT_DEF(SMX, 0x00000001, 0, RTE_REG_ECX,  6)
+	FEAT_DEF(EIST, 0x00000001, 0, RTE_REG_ECX,  7)
+	FEAT_DEF(TM2, 0x00000001, 0, RTE_REG_ECX,  8)
+	FEAT_DEF(SSSE3, 0x00000001, 0, RTE_REG_ECX,  9)
+	FEAT_DEF(CNXT_ID, 0x00000001, 0, RTE_REG_ECX, 10)
+	FEAT_DEF(FMA, 0x00000001, 0, RTE_REG_ECX, 12)
+	FEAT_DEF(CMPXCHG16B, 0x00000001, 0, RTE_REG_ECX, 13)
+	FEAT_DEF(XTPR, 0x00000001, 0, RTE_REG_ECX, 14)
+	FEAT_DEF(PDCM, 0x00000001, 0, RTE_REG_ECX, 15)
+	FEAT_DEF(PCID, 0x00000001, 0, RTE_REG_ECX, 17)
+	FEAT_DEF(DCA, 0x00000001, 0, RTE_REG_ECX, 18)
+	FEAT_DEF(SSE4_1, 0x00000001, 0, RTE_REG_ECX, 19)
+	FEAT_DEF(SSE4_2, 0x00000001, 0, RTE_REG_ECX, 20)
+	FEAT_DEF(X2APIC, 0x00000001, 0, RTE_REG_ECX, 21)
+	FEAT_DEF(MOVBE, 0x00000001, 0, RTE_REG_ECX, 22)
+	FEAT_DEF(POPCNT, 0x00000001, 0, RTE_REG_ECX, 23)
+	FEAT_DEF(TSC_DEADLINE, 0x00000001, 0, RTE_REG_ECX, 24)
+	FEAT_DEF(AES, 0x00000001, 0, RTE_REG_ECX, 25)
+	FEAT_DEF(XSAVE, 0x00000001, 0, RTE_REG_ECX, 26)
+	FEAT_DEF(OSXSAVE, 0x00000001, 0, RTE_REG_ECX, 27)
+	FEAT_DEF(AVX, 0x00000001, 0, RTE_REG_ECX, 28)
+	FEAT_DEF(F16C, 0x00000001, 0, RTE_REG_ECX, 29)
+	FEAT_DEF(RDRAND, 0x00000001, 0, RTE_REG_ECX, 30)
+
+	FEAT_DEF(FPU, 0x00000001, 0, RTE_REG_EDX,  0)
+	FEAT_DEF(VME, 0x00000001, 0, RTE_REG_EDX,  1)
+	FEAT_DEF(DE, 0x00000001, 0, RTE_REG_EDX,  2)
+	FEAT_DEF(PSE, 0x00000001, 0, RTE_REG_EDX,  3)
+	FEAT_DEF(TSC, 0x00000001, 0, RTE_REG_EDX,  4)
+	FEAT_DEF(MSR, 0x00000001, 0, RTE_REG_EDX,  5)
+	FEAT_DEF(PAE, 0x00000001, 0, RTE_REG_EDX,  6)
+	FEAT_DEF(MCE, 0x00000001, 0, RTE_REG_EDX,  7)
+	FEAT_DEF(CX8, 0x00000001, 0, RTE_REG_EDX,  8)
+	FEAT_DEF(APIC, 0x00000001, 0, RTE_REG_EDX,  9)
+	FEAT_DEF(SEP, 0x00000001, 0, RTE_REG_EDX, 11)
+	FEAT_DEF(MTRR, 0x00000001, 0, RTE_REG_EDX, 12)
+	FEAT_DEF(PGE, 0x00000001, 0, RTE_REG_EDX, 13)
+	FEAT_DEF(MCA, 0x00000001, 0, RTE_REG_EDX, 14)
+	FEAT_DEF(CMOV, 0x00000001, 0, RTE_REG_EDX, 15)
+	FEAT_DEF(PAT, 0x00000001, 0, RTE_REG_EDX, 16)
+	FEAT_DEF(PSE36, 0x00000001, 0, RTE_REG_EDX, 17)
+	FEAT_DEF(PSN, 0x00000001, 0, RTE_REG_EDX, 18)
+	FEAT_DEF(CLFSH, 0x00000001, 0, RTE_REG_EDX, 19)
+	FEAT_DEF(DS, 0x00000001, 0, RTE_REG_EDX, 21)
+	FEAT_DEF(ACPI, 0x00000001, 0, RTE_REG_EDX, 22)
+	FEAT_DEF(MMX, 0x00000001, 0, RTE_REG_EDX, 23)
+	FEAT_DEF(FXSR, 0x00000001, 0, RTE_REG_EDX, 24)
+	FEAT_DEF(SSE, 0x00000001, 0, RTE_REG_EDX, 25)
+	FEAT_DEF(SSE2, 0x00000001, 0, RTE_REG_EDX, 26)
+	FEAT_DEF(SS, 0x00000001, 0, RTE_REG_EDX, 27)
+	FEAT_DEF(HTT, 0x00000001, 0, RTE_REG_EDX, 28)
+	FEAT_DEF(TM, 0x00000001, 0, RTE_REG_EDX, 29)
+	FEAT_DEF(PBE, 0x00000001, 0, RTE_REG_EDX, 31)
+
+	FEAT_DEF(DIGTEMP, 0x00000006, 0, RTE_REG_EAX,  0)
+	FEAT_DEF(TRBOBST, 0x00000006, 0, RTE_REG_EAX,  1)
+	FEAT_DEF(ARAT, 0x00000006, 0, RTE_REG_EAX,  2)
+	FEAT_DEF(PLN, 0x00000006, 0, RTE_REG_EAX,  4)
+	FEAT_DEF(ECMD, 0x00000006, 0, RTE_REG_EAX,  5)
+	FEAT_DEF(PTM, 0x00000006, 0, RTE_REG_EAX,  6)
+
+	FEAT_DEF(MPERF_APERF_MSR, 0x00000006, 0, RTE_REG_ECX,  0)
+	FEAT_DEF(ACNT2, 0x00000006, 0, RTE_REG_ECX,  1)
+	FEAT_DEF(ENERGY_EFF, 0x00000006, 0, RTE_REG_ECX,  3)
+
+	FEAT_DEF(FSGSBASE, 0x00000007, 0, RTE_REG_EBX,  0)
+	FEAT_DEF(BMI1, 0x00000007, 0, RTE_REG_EBX,  2)
+	FEAT_DEF(HLE, 0x00000007, 0, RTE_REG_EBX,  4)
+	FEAT_DEF(AVX2, 0x00000007, 0, RTE_REG_EBX,  5)
+	FEAT_DEF(SMEP, 0x00000007, 0, RTE_REG_EBX,  6)
+	FEAT_DEF(BMI2, 0x00000007, 0, RTE_REG_EBX,  7)
+	FEAT_DEF(ERMS, 0x00000007, 0, RTE_REG_EBX,  8)
+	FEAT_DEF(INVPCID, 0x00000007, 0, RTE_REG_EBX, 10)
+	FEAT_DEF(RTM, 0x00000007, 0, RTE_REG_EBX, 11)
+
+	FEAT_DEF(LAHF_SAHF, 0x80000001, 0, RTE_REG_ECX,  0)
+	FEAT_DEF(LZCNT, 0x80000001, 0, RTE_REG_ECX,  4)
+
+	FEAT_DEF(SYSCALL, 0x80000001, 0, RTE_REG_EDX, 11)
+	FEAT_DEF(XD, 0x80000001, 0, RTE_REG_EDX, 20)
+	FEAT_DEF(1GB_PG, 0x80000001, 0, RTE_REG_EDX, 26)
+	FEAT_DEF(RDTSCP, 0x80000001, 0, RTE_REG_EDX, 27)
+	FEAT_DEF(EM64T, 0x80000001, 0, RTE_REG_EDX, 29)
+
+	FEAT_DEF(INVTSC, 0x80000007, 0, RTE_REG_EDX,  8)
 };
 
 static inline void
@@ -257,18 +257,18 @@ rte_cpu_get_features(uint32_t leaf, uint32_t subleaf, cpuid_registers_t out)
 #if defined(__i386__) && defined(__PIC__)
     /* %ebx is a forbidden register if we compile with -fPIC or -fPIE */
     asm volatile("movl %%ebx,%0 ; cpuid ; xchgl %%ebx,%0"
-		 : "=r" (out[REG_EBX]),
-		   "=a" (out[REG_EAX]),
-		   "=c" (out[REG_ECX]),
-		   "=d" (out[REG_EDX])
+		 : "=r" (out[RTE_REG_EBX]),
+		   "=a" (out[RTE_REG_EAX]),
+		   "=c" (out[RTE_REG_ECX]),
+		   "=d" (out[RTE_REG_EDX])
 		 : "a" (leaf), "c" (subleaf));
 #else
 
     asm volatile("cpuid"
-		 : "=a" (out[REG_EAX]),
-		   "=b" (out[REG_EBX]),
-		   "=c" (out[REG_ECX]),
-		   "=d" (out[REG_EDX])
+		 : "=a" (out[RTE_REG_EAX]),
+		   "=b" (out[RTE_REG_EBX]),
+		   "=c" (out[RTE_REG_ECX]),
+		   "=d" (out[RTE_REG_EDX])
 		 : "a" (leaf), "c" (subleaf));
 
 #endif
@@ -292,8 +292,8 @@ rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
 		return -EFAULT;
 
 	rte_cpu_get_features(feat->leaf & 0xffff0000, 0, regs);
-	if (((regs[REG_EAX] ^ feat->leaf) & 0xffff0000) ||
-	      regs[REG_EAX] < feat->leaf)
+	if (((regs[RTE_REG_EAX] ^ feat->leaf) & 0xffff0000) ||
+	      regs[RTE_REG_EAX] < feat->leaf)
 		return 0;
 
 	/* get the cpuid leaf containing the desired feature */
-- 
1.9.3

Re: [dpdk-dev] [PATCH 3/3] librte_eal/common: Fix redeclaration of enumerator ‘REG_EAX’

[Qiu, Michael]

On 3/5/2015 9:36 PM, David Marchand wrote:
> On Thu, Mar 5, 2015 at 2:23 PM, Bruce Richardson
> <bruce.richardson@intel.com <mailto:bruce.richardson@intel.com>> wrote:
>
>     On Thu, Mar 05, 2015 at 09:15:39PM +0800, Michael Qiu wrote:
>     > include/rte_cpuflags.h:154:2: error: redeclaration of enumerator
>     ‘REG_EAX’
>     > In file included from /usr/include/signal.h:358:0,
>     >                  from /usr/include/sys/wait.h:30,
>     >                  from /root/dpdk/app/test/test_mp_secondary.c:50:
>     > /usr/include/sys/ucontext.h:180:3: note: previous definition of
>     ‘REG_EAX’ was here
>     >
>     > In i686, from REG_EAX to REG_EDX are all defined in
>     >       /usr/include/sys/ucontext.h
>
>
> Well, this is the same for x86_64.

Yes, but for some reason, it was not include, see /usr/include/signal.h:358

# include <bits/sigstack.h>
# if defined __USE_XOPEN || defined __USE_XOPEN2K8
/* This will define `ucontext_t' and `mcontext_t'.  */
#  include <sys/ucontext.h>
# endif

So only if __USE_XOPEN or __USE_XOPEN2K8 been defined will include 
<sys/ucontext.h>

Thanks,
Michael
>
> $ grep -rl '\<REG_EAX\>' /usr/include/
> /usr/include/x86_64-linux-gnu/sys/ucontext.h
>
> $ ls -l /usr/include/sys/ucontext.h 
> lrwxrwxrwx 1 root root 34 Feb 22 12:45 /usr/include/sys/ucontext.h ->
> ../x86_64-linux-gnu/sys/ucontext.h
>
> So I am not sure I understand why we redefine stuff already available
> from the toolchain.
> Rather than prefixing, I think we should get rid of this and include
> the right header.
>
>
> -- 
> David Marchand 

Re: [dpdk-dev] [PATCH 3/3 v2] librte_eal/common: Fix redeclaration of enumerator ‘REG_EAX’

[David Marchand]

On Thu, Mar 5, 2015 at 2:50 PM, Michael Qiu <michael.qiu@intel.com> wrote:

> include/rte_cpuflags.h:154:2: error: redeclaration of enumerator ‘REG_EAX’
> In file included from /usr/include/signal.h:358:0,
>                  from /usr/include/sys/wait.h:30,
>                  from /root/dpdk/app/test/test_mp_secondary.c:50:
> /usr/include/sys/ucontext.h:180:3: note: previous definition of ‘REG_EAX’
> was here
>
> In i686, from REG_EAX to REG_EDX are all defined in
>         /usr/include/sys/ucontext.h
>
> Rename to CPU_REG_EAX to avoid this issue.
>
> Signed-off-by: Michael Qou <michael.qiu@intel.com>
>

NAK.

You did not answer my question.
This mail title is broken anyway.


-- 
David Marchand

[dpdk-dev] [PATCH 3/3 v3] =?UTF-8?q?librte=5Feal/common:=20Fix=20redeclaration=20of?= =?UTF-8?q?=20enumerator=20=E2=80=98REG=5FEAX=E2=80=99?=

[Michael Qiu]

include/rte_cpuflags.h:154:2: error: redeclaration of enumerator ‘REG_EAX’
In file included from /usr/include/signal.h:358:0,
                 from /usr/include/sys/wait.h:30,
                 from /root/dpdk/app/test/test_mp_secondary.c:50:
/usr/include/sys/ucontext.h:180:3: note: previous definition of ‘REG_EAX’ was here

In i686, from REG_EAX to REG_EDX are all defined in
	/usr/include/sys/ucontext.h

Rename to CPU_REG_EAX to avoid this issue.

Signed-off-by: Michael Qiu <michael.qiu@intel.com>
---
v3 --> v2:
	Fix signed-off-by field
v2 --> v1:
	rename CPU_REG_EAX to RTE_REG_EAX

 .../common/include/arch/x86/rte_cpuflags.h         | 210 ++++++++++-----------
 1 file changed, 105 insertions(+), 105 deletions(-)

diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
index a58dd7b..dd56553 100644
--- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
+++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
@@ -151,104 +151,104 @@ enum rte_cpu_flag_t {
 };
 
 enum cpu_register_t {
-	REG_EAX = 0,
-	REG_EBX,
-	REG_ECX,
-	REG_EDX,
+	RTE_REG_EAX = 0,
+	RTE_REG_EBX,
+	RTE_REG_ECX,
+	RTE_REG_EDX,
 };
 
 static const struct feature_entry cpu_feature_table[] = {
-	FEAT_DEF(SSE3, 0x00000001, 0, REG_ECX,  0)
-	FEAT_DEF(PCLMULQDQ, 0x00000001, 0, REG_ECX,  1)
-	FEAT_DEF(DTES64, 0x00000001, 0, REG_ECX,  2)
-	FEAT_DEF(MONITOR, 0x00000001, 0, REG_ECX,  3)
-	FEAT_DEF(DS_CPL, 0x00000001, 0, REG_ECX,  4)
-	FEAT_DEF(VMX, 0x00000001, 0, REG_ECX,  5)
-	FEAT_DEF(SMX, 0x00000001, 0, REG_ECX,  6)
-	FEAT_DEF(EIST, 0x00000001, 0, REG_ECX,  7)
-	FEAT_DEF(TM2, 0x00000001, 0, REG_ECX,  8)
-	FEAT_DEF(SSSE3, 0x00000001, 0, REG_ECX,  9)
-	FEAT_DEF(CNXT_ID, 0x00000001, 0, REG_ECX, 10)
-	FEAT_DEF(FMA, 0x00000001, 0, REG_ECX, 12)
-	FEAT_DEF(CMPXCHG16B, 0x00000001, 0, REG_ECX, 13)
-	FEAT_DEF(XTPR, 0x00000001, 0, REG_ECX, 14)
-	FEAT_DEF(PDCM, 0x00000001, 0, REG_ECX, 15)
-	FEAT_DEF(PCID, 0x00000001, 0, REG_ECX, 17)
-	FEAT_DEF(DCA, 0x00000001, 0, REG_ECX, 18)
-	FEAT_DEF(SSE4_1, 0x00000001, 0, REG_ECX, 19)
-	FEAT_DEF(SSE4_2, 0x00000001, 0, REG_ECX, 20)
-	FEAT_DEF(X2APIC, 0x00000001, 0, REG_ECX, 21)
-	FEAT_DEF(MOVBE, 0x00000001, 0, REG_ECX, 22)
-	FEAT_DEF(POPCNT, 0x00000001, 0, REG_ECX, 23)
-	FEAT_DEF(TSC_DEADLINE, 0x00000001, 0, REG_ECX, 24)
-	FEAT_DEF(AES, 0x00000001, 0, REG_ECX, 25)
-	FEAT_DEF(XSAVE, 0x00000001, 0, REG_ECX, 26)
-	FEAT_DEF(OSXSAVE, 0x00000001, 0, REG_ECX, 27)
-	FEAT_DEF(AVX, 0x00000001, 0, REG_ECX, 28)
-	FEAT_DEF(F16C, 0x00000001, 0, REG_ECX, 29)
-	FEAT_DEF(RDRAND, 0x00000001, 0, REG_ECX, 30)
-
-	FEAT_DEF(FPU, 0x00000001, 0, REG_EDX,  0)
-	FEAT_DEF(VME, 0x00000001, 0, REG_EDX,  1)
-	FEAT_DEF(DE, 0x00000001, 0, REG_EDX,  2)
-	FEAT_DEF(PSE, 0x00000001, 0, REG_EDX,  3)
-	FEAT_DEF(TSC, 0x00000001, 0, REG_EDX,  4)
-	FEAT_DEF(MSR, 0x00000001, 0, REG_EDX,  5)
-	FEAT_DEF(PAE, 0x00000001, 0, REG_EDX,  6)
-	FEAT_DEF(MCE, 0x00000001, 0, REG_EDX,  7)
-	FEAT_DEF(CX8, 0x00000001, 0, REG_EDX,  8)
-	FEAT_DEF(APIC, 0x00000001, 0, REG_EDX,  9)
-	FEAT_DEF(SEP, 0x00000001, 0, REG_EDX, 11)
-	FEAT_DEF(MTRR, 0x00000001, 0, REG_EDX, 12)
-	FEAT_DEF(PGE, 0x00000001, 0, REG_EDX, 13)
-	FEAT_DEF(MCA, 0x00000001, 0, REG_EDX, 14)
-	FEAT_DEF(CMOV, 0x00000001, 0, REG_EDX, 15)
-	FEAT_DEF(PAT, 0x00000001, 0, REG_EDX, 16)
-	FEAT_DEF(PSE36, 0x00000001, 0, REG_EDX, 17)
-	FEAT_DEF(PSN, 0x00000001, 0, REG_EDX, 18)
-	FEAT_DEF(CLFSH, 0x00000001, 0, REG_EDX, 19)
-	FEAT_DEF(DS, 0x00000001, 0, REG_EDX, 21)
-	FEAT_DEF(ACPI, 0x00000001, 0, REG_EDX, 22)
-	FEAT_DEF(MMX, 0x00000001, 0, REG_EDX, 23)
-	FEAT_DEF(FXSR, 0x00000001, 0, REG_EDX, 24)
-	FEAT_DEF(SSE, 0x00000001, 0, REG_EDX, 25)
-	FEAT_DEF(SSE2, 0x00000001, 0, REG_EDX, 26)
-	FEAT_DEF(SS, 0x00000001, 0, REG_EDX, 27)
-	FEAT_DEF(HTT, 0x00000001, 0, REG_EDX, 28)
-	FEAT_DEF(TM, 0x00000001, 0, REG_EDX, 29)
-	FEAT_DEF(PBE, 0x00000001, 0, REG_EDX, 31)
-
-	FEAT_DEF(DIGTEMP, 0x00000006, 0, REG_EAX,  0)
-	FEAT_DEF(TRBOBST, 0x00000006, 0, REG_EAX,  1)
-	FEAT_DEF(ARAT, 0x00000006, 0, REG_EAX,  2)
-	FEAT_DEF(PLN, 0x00000006, 0, REG_EAX,  4)
-	FEAT_DEF(ECMD, 0x00000006, 0, REG_EAX,  5)
-	FEAT_DEF(PTM, 0x00000006, 0, REG_EAX,  6)
-
-	FEAT_DEF(MPERF_APERF_MSR, 0x00000006, 0, REG_ECX,  0)
-	FEAT_DEF(ACNT2, 0x00000006, 0, REG_ECX,  1)
-	FEAT_DEF(ENERGY_EFF, 0x00000006, 0, REG_ECX,  3)
-
-	FEAT_DEF(FSGSBASE, 0x00000007, 0, REG_EBX,  0)
-	FEAT_DEF(BMI1, 0x00000007, 0, REG_EBX,  2)
-	FEAT_DEF(HLE, 0x00000007, 0, REG_EBX,  4)
-	FEAT_DEF(AVX2, 0x00000007, 0, REG_EBX,  5)
-	FEAT_DEF(SMEP, 0x00000007, 0, REG_EBX,  6)
-	FEAT_DEF(BMI2, 0x00000007, 0, REG_EBX,  7)
-	FEAT_DEF(ERMS, 0x00000007, 0, REG_EBX,  8)
-	FEAT_DEF(INVPCID, 0x00000007, 0, REG_EBX, 10)
-	FEAT_DEF(RTM, 0x00000007, 0, REG_EBX, 11)
-
-	FEAT_DEF(LAHF_SAHF, 0x80000001, 0, REG_ECX,  0)
-	FEAT_DEF(LZCNT, 0x80000001, 0, REG_ECX,  4)
-
-	FEAT_DEF(SYSCALL, 0x80000001, 0, REG_EDX, 11)
-	FEAT_DEF(XD, 0x80000001, 0, REG_EDX, 20)
-	FEAT_DEF(1GB_PG, 0x80000001, 0, REG_EDX, 26)
-	FEAT_DEF(RDTSCP, 0x80000001, 0, REG_EDX, 27)
-	FEAT_DEF(EM64T, 0x80000001, 0, REG_EDX, 29)
-
-	FEAT_DEF(INVTSC, 0x80000007, 0, REG_EDX,  8)
+	FEAT_DEF(SSE3, 0x00000001, 0, RTE_REG_ECX,  0)
+	FEAT_DEF(PCLMULQDQ, 0x00000001, 0, RTE_REG_ECX,  1)
+	FEAT_DEF(DTES64, 0x00000001, 0, RTE_REG_ECX,  2)
+	FEAT_DEF(MONITOR, 0x00000001, 0, RTE_REG_ECX,  3)
+	FEAT_DEF(DS_CPL, 0x00000001, 0, RTE_REG_ECX,  4)
+	FEAT_DEF(VMX, 0x00000001, 0, RTE_REG_ECX,  5)
+	FEAT_DEF(SMX, 0x00000001, 0, RTE_REG_ECX,  6)
+	FEAT_DEF(EIST, 0x00000001, 0, RTE_REG_ECX,  7)
+	FEAT_DEF(TM2, 0x00000001, 0, RTE_REG_ECX,  8)
+	FEAT_DEF(SSSE3, 0x00000001, 0, RTE_REG_ECX,  9)
+	FEAT_DEF(CNXT_ID, 0x00000001, 0, RTE_REG_ECX, 10)
+	FEAT_DEF(FMA, 0x00000001, 0, RTE_REG_ECX, 12)
+	FEAT_DEF(CMPXCHG16B, 0x00000001, 0, RTE_REG_ECX, 13)
+	FEAT_DEF(XTPR, 0x00000001, 0, RTE_REG_ECX, 14)
+	FEAT_DEF(PDCM, 0x00000001, 0, RTE_REG_ECX, 15)
+	FEAT_DEF(PCID, 0x00000001, 0, RTE_REG_ECX, 17)
+	FEAT_DEF(DCA, 0x00000001, 0, RTE_REG_ECX, 18)
+	FEAT_DEF(SSE4_1, 0x00000001, 0, RTE_REG_ECX, 19)
+	FEAT_DEF(SSE4_2, 0x00000001, 0, RTE_REG_ECX, 20)
+	FEAT_DEF(X2APIC, 0x00000001, 0, RTE_REG_ECX, 21)
+	FEAT_DEF(MOVBE, 0x00000001, 0, RTE_REG_ECX, 22)
+	FEAT_DEF(POPCNT, 0x00000001, 0, RTE_REG_ECX, 23)
+	FEAT_DEF(TSC_DEADLINE, 0x00000001, 0, RTE_REG_ECX, 24)
+	FEAT_DEF(AES, 0x00000001, 0, RTE_REG_ECX, 25)
+	FEAT_DEF(XSAVE, 0x00000001, 0, RTE_REG_ECX, 26)
+	FEAT_DEF(OSXSAVE, 0x00000001, 0, RTE_REG_ECX, 27)
+	FEAT_DEF(AVX, 0x00000001, 0, RTE_REG_ECX, 28)
+	FEAT_DEF(F16C, 0x00000001, 0, RTE_REG_ECX, 29)
+	FEAT_DEF(RDRAND, 0x00000001, 0, RTE_REG_ECX, 30)
+
+	FEAT_DEF(FPU, 0x00000001, 0, RTE_REG_EDX,  0)
+	FEAT_DEF(VME, 0x00000001, 0, RTE_REG_EDX,  1)
+	FEAT_DEF(DE, 0x00000001, 0, RTE_REG_EDX,  2)
+	FEAT_DEF(PSE, 0x00000001, 0, RTE_REG_EDX,  3)
+	FEAT_DEF(TSC, 0x00000001, 0, RTE_REG_EDX,  4)
+	FEAT_DEF(MSR, 0x00000001, 0, RTE_REG_EDX,  5)
+	FEAT_DEF(PAE, 0x00000001, 0, RTE_REG_EDX,  6)
+	FEAT_DEF(MCE, 0x00000001, 0, RTE_REG_EDX,  7)
+	FEAT_DEF(CX8, 0x00000001, 0, RTE_REG_EDX,  8)
+	FEAT_DEF(APIC, 0x00000001, 0, RTE_REG_EDX,  9)
+	FEAT_DEF(SEP, 0x00000001, 0, RTE_REG_EDX, 11)
+	FEAT_DEF(MTRR, 0x00000001, 0, RTE_REG_EDX, 12)
+	FEAT_DEF(PGE, 0x00000001, 0, RTE_REG_EDX, 13)
+	FEAT_DEF(MCA, 0x00000001, 0, RTE_REG_EDX, 14)
+	FEAT_DEF(CMOV, 0x00000001, 0, RTE_REG_EDX, 15)
+	FEAT_DEF(PAT, 0x00000001, 0, RTE_REG_EDX, 16)
+	FEAT_DEF(PSE36, 0x00000001, 0, RTE_REG_EDX, 17)
+	FEAT_DEF(PSN, 0x00000001, 0, RTE_REG_EDX, 18)
+	FEAT_DEF(CLFSH, 0x00000001, 0, RTE_REG_EDX, 19)
+	FEAT_DEF(DS, 0x00000001, 0, RTE_REG_EDX, 21)
+	FEAT_DEF(ACPI, 0x00000001, 0, RTE_REG_EDX, 22)
+	FEAT_DEF(MMX, 0x00000001, 0, RTE_REG_EDX, 23)
+	FEAT_DEF(FXSR, 0x00000001, 0, RTE_REG_EDX, 24)
+	FEAT_DEF(SSE, 0x00000001, 0, RTE_REG_EDX, 25)
+	FEAT_DEF(SSE2, 0x00000001, 0, RTE_REG_EDX, 26)
+	FEAT_DEF(SS, 0x00000001, 0, RTE_REG_EDX, 27)
+	FEAT_DEF(HTT, 0x00000001, 0, RTE_REG_EDX, 28)
+	FEAT_DEF(TM, 0x00000001, 0, RTE_REG_EDX, 29)
+	FEAT_DEF(PBE, 0x00000001, 0, RTE_REG_EDX, 31)
+
+	FEAT_DEF(DIGTEMP, 0x00000006, 0, RTE_REG_EAX,  0)
+	FEAT_DEF(TRBOBST, 0x00000006, 0, RTE_REG_EAX,  1)
+	FEAT_DEF(ARAT, 0x00000006, 0, RTE_REG_EAX,  2)
+	FEAT_DEF(PLN, 0x00000006, 0, RTE_REG_EAX,  4)
+	FEAT_DEF(ECMD, 0x00000006, 0, RTE_REG_EAX,  5)
+	FEAT_DEF(PTM, 0x00000006, 0, RTE_REG_EAX,  6)
+
+	FEAT_DEF(MPERF_APERF_MSR, 0x00000006, 0, RTE_REG_ECX,  0)
+	FEAT_DEF(ACNT2, 0x00000006, 0, RTE_REG_ECX,  1)
+	FEAT_DEF(ENERGY_EFF, 0x00000006, 0, RTE_REG_ECX,  3)
+
+	FEAT_DEF(FSGSBASE, 0x00000007, 0, RTE_REG_EBX,  0)
+	FEAT_DEF(BMI1, 0x00000007, 0, RTE_REG_EBX,  2)
+	FEAT_DEF(HLE, 0x00000007, 0, RTE_REG_EBX,  4)
+	FEAT_DEF(AVX2, 0x00000007, 0, RTE_REG_EBX,  5)
+	FEAT_DEF(SMEP, 0x00000007, 0, RTE_REG_EBX,  6)
+	FEAT_DEF(BMI2, 0x00000007, 0, RTE_REG_EBX,  7)
+	FEAT_DEF(ERMS, 0x00000007, 0, RTE_REG_EBX,  8)
+	FEAT_DEF(INVPCID, 0x00000007, 0, RTE_REG_EBX, 10)
+	FEAT_DEF(RTM, 0x00000007, 0, RTE_REG_EBX, 11)
+
+	FEAT_DEF(LAHF_SAHF, 0x80000001, 0, RTE_REG_ECX,  0)
+	FEAT_DEF(LZCNT, 0x80000001, 0, RTE_REG_ECX,  4)
+
+	FEAT_DEF(SYSCALL, 0x80000001, 0, RTE_REG_EDX, 11)
+	FEAT_DEF(XD, 0x80000001, 0, RTE_REG_EDX, 20)
+	FEAT_DEF(1GB_PG, 0x80000001, 0, RTE_REG_EDX, 26)
+	FEAT_DEF(RDTSCP, 0x80000001, 0, RTE_REG_EDX, 27)
+	FEAT_DEF(EM64T, 0x80000001, 0, RTE_REG_EDX, 29)
+
+	FEAT_DEF(INVTSC, 0x80000007, 0, RTE_REG_EDX,  8)
 };
 
 static inline void
@@ -257,18 +257,18 @@ rte_cpu_get_features(uint32_t leaf, uint32_t subleaf, cpuid_registers_t out)
 #if defined(__i386__) && defined(__PIC__)
     /* %ebx is a forbidden register if we compile with -fPIC or -fPIE */
     asm volatile("movl %%ebx,%0 ; cpuid ; xchgl %%ebx,%0"
-		 : "=r" (out[REG_EBX]),
-		   "=a" (out[REG_EAX]),
-		   "=c" (out[REG_ECX]),
-		   "=d" (out[REG_EDX])
+		 : "=r" (out[RTE_REG_EBX]),
+		   "=a" (out[RTE_REG_EAX]),
+		   "=c" (out[RTE_REG_ECX]),
+		   "=d" (out[RTE_REG_EDX])
 		 : "a" (leaf), "c" (subleaf));
 #else
 
     asm volatile("cpuid"
-		 : "=a" (out[REG_EAX]),
-		   "=b" (out[REG_EBX]),
-		   "=c" (out[REG_ECX]),
-		   "=d" (out[REG_EDX])
+		 : "=a" (out[RTE_REG_EAX]),
+		   "=b" (out[RTE_REG_EBX]),
+		   "=c" (out[RTE_REG_ECX]),
+		   "=d" (out[RTE_REG_EDX])
 		 : "a" (leaf), "c" (subleaf));
 
 #endif
@@ -292,8 +292,8 @@ rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
 		return -EFAULT;
 
 	rte_cpu_get_features(feat->leaf & 0xffff0000, 0, regs);
-	if (((regs[REG_EAX] ^ feat->leaf) & 0xffff0000) ||
-	      regs[REG_EAX] < feat->leaf)
+	if (((regs[RTE_REG_EAX] ^ feat->leaf) & 0xffff0000) ||
+	      regs[RTE_REG_EAX] < feat->leaf)
 		return 0;
 
 	/* get the cpuid leaf containing the desired feature */
-- 
1.9.3

[dpdk-dev] [PATCH 2/3 v2] app/test: Fix size_t printf format issue

[Michael Qiu]

test_hash.c: In function ‘test_crc32_hash_alg_equiv’:
error: format ‘%lu’ expects argument of type ‘long unsigned int’,
but argument 2 has type ‘size_t’ [-Werror=format]

According to C99, for size_t type should use format "%zu"

Signed-off-by: Michael Qiu <michael.qiu@intel.com>
---
v2 --> v1:
	typo fix of "format" in commit log and title

 app/test/test_hash.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/app/test/test_hash.c b/app/test/test_hash.c
index 653dd86..c489b8b 100644
--- a/app/test/test_hash.c
+++ b/app/test/test_hash.c
@@ -226,7 +226,7 @@ test_crc32_hash_alg_equiv(void)
 	if (i == CRC32_ITERATIONS)
 		return 0;
 
-	printf("Failed test data (hex, %lu bytes total):\n", data_len);
+	printf("Failed test data (hex, %zu bytes total):\n", data_len);
 	for (j = 0; j < data_len; j++)
 		printf("%02X%c", ((uint8_t *)data64)[j],
 				((j+1) % 16 == 0 || j == data_len - 1) ? '\n' : ' ');
-- 
1.9.3

Re: [dpdk-dev] [PATCH 3/3 v2] librte_eal/common: Fix redeclaration of enumerator ‘REG_EAX’

[Qiu, Michael]

On 3/5/2015 9:54 PM, David Marchand wrote:
> On Thu, Mar 5, 2015 at 2:50 PM, Michael Qiu <michael.qiu@intel.com
> <mailto:michael.qiu@intel.com>> wrote:
>
>     include/rte_cpuflags.h:154:2: error: redeclaration of enumerator
>     ‘REG_EAX’
>     In file included from /usr/include/signal.h:358:0,
>                      from /usr/include/sys/wait.h:30,
>                      from /root/dpdk/app/test/test_mp_secondary.c:50:
>     /usr/include/sys/ucontext.h:180:3: note: previous definition of
>     ‘REG_EAX’ was here
>
>     In i686, from REG_EAX to REG_EDX are all defined in
>             /usr/include/sys/ucontext.h
>
>     Rename to CPU_REG_EAX to avoid this issue.
>
>     Signed-off-by: Michael Qou <michael.qiu@intel.com
>     <mailto:michael.qiu@intel.com>>
>
>
> NAK.
>

I have answered in you last thread, please check the mail.

Yes, but for some reason, it was not include, see /usr/include/signal.h:358

# include <bits/sigstack.h>
# if defined __USE_XOPEN || defined __USE_XOPEN2K8
/* This will define `ucontext_t' and `mcontext_t'.  */
#  include <sys/ucontext.h>
# endif

So only if __USE_XOPEN or __USE_XOPEN2K8 been defined will include 
<sys/ucontext.h>


Why NAK?

Thanks,
Michael
> You did not answer my question.
> This mail title is broken anyway.
>
>
> -- 
> David Marchand

Re: [dpdk-dev] [PATCH 3/3 v2] librte_eal/common: Fix redeclaration of enumerator ‘REG_EAX’

[Thomas Monjalon]

2015-03-05 14:03, Qiu, Michael:
> On 3/5/2015 9:54 PM, David Marchand wrote:
> > On Thu, Mar 5, 2015 at 2:50 PM, Michael Qiu <michael.qiu@intel.com
> > <mailto:michael.qiu@intel.com>> wrote:
> >
> >     include/rte_cpuflags.h:154:2: error: redeclaration of enumerator
> >     ‘REG_EAX’
> >     In file included from /usr/include/signal.h:358:0,
> >                      from /usr/include/sys/wait.h:30,
> >                      from /root/dpdk/app/test/test_mp_secondary.c:50:
> >     /usr/include/sys/ucontext.h:180:3: note: previous definition of
> >     ‘REG_EAX’ was here
> >
> >     In i686, from REG_EAX to REG_EDX are all defined in
> >             /usr/include/sys/ucontext.h
> >
> >     Rename to CPU_REG_EAX to avoid this issue.
> >
> >     Signed-off-by: Michael Qou <michael.qiu@intel.com
> >     <mailto:michael.qiu@intel.com>>
> >
> >
> > NAK.
> >
> 
> I have answered in you last thread, please check the mail.
> 
> Yes, but for some reason, it was not include, see /usr/include/signal.h:358
> 
> # include <bits/sigstack.h>
> # if defined __USE_XOPEN || defined __USE_XOPEN2K8
> /* This will define `ucontext_t' and `mcontext_t'.  */
> #  include <sys/ucontext.h>
> # endif
> 
> So only if __USE_XOPEN or __USE_XOPEN2K8 been defined will include 
> <sys/ucontext.h>

So try to define USE_XOPEN.

> Why NAK?

Because it seems you didn't really try to include system headers.
We must avoid redefine existing symbols. That's why this bug happens.
Michael, thanks for trying to fix this issue. It's appreciated even if
the first solution is refused.

Re: [dpdk-dev] [PATCH 1/3] librte_hash: Fix unsupported instruction `crc32' in i686 platform

[Yerden Zhumabekov]

Hi Michael,

Thanks for this patch, in fact I didn't try to compile it on i686 when
developing original software fallback for CRC32.

I think if we want to make code compilable as wide as possible, we
should compile out all SSE4.2 instructions. As to the patch, we may
compile out 'crc32l' instruction emitting code if the arch is not x86.
This concerns two functions: crc32c_sse42_u32() and
crc32c_sse42_u64_mimic().

The compile check might be something like this:

#if defined(RTE_ARCH_I686) || defined(RTE_ARCH_X86_64)
#endif

Otherwise, the patch looks good.

05.03.2015 19:15, Michael Qiu пишет:
> CC rte_hash.o
> Error: unsupported instruction `crc32'
>
> The root cause is that i686 platform does not support 'crc32q'
> Need make it only available in x86_64 platform
>
> Signed-off-by: Michael Qiu <michael.qiu@intel.com>
> ---
>  lib/librte_hash/rte_hash_crc.h | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/lib/librte_hash/rte_hash_crc.h b/lib/librte_hash/rte_hash_crc.h
> index d28bb2a..4e9546f 100644
> --- a/lib/librte_hash/rte_hash_crc.h
> +++ b/lib/librte_hash/rte_hash_crc.h
> @@ -374,6 +374,7 @@ crc32c_sse42_u32(uint32_t data, uint32_t init_val)
>  	return init_val;
>  }
>  
> +#ifdef RTE_ARCH_X86_64
>  static inline uint32_t
>  crc32c_sse42_u64(uint64_t data, uint64_t init_val)
>  {
> @@ -383,6 +384,7 @@ crc32c_sse42_u64(uint64_t data, uint64_t init_val)
>  			: [data] "rm" (data));
>  	return init_val;
>  }
> +#endif
>  
>  static inline uint32_t
>  crc32c_sse42_u64_mimic(uint64_t data, uint64_t init_val)
> @@ -476,8 +478,10 @@ rte_hash_crc_4byte(uint32_t data, uint32_t init_val)
>  static inline uint32_t
>  rte_hash_crc_8byte(uint64_t data, uint32_t init_val)
>  {
> +#ifdef RTE_ARCH_X86_64
>  	if (likely(crc32_alg == CRC32_SSE42_x64))
>  		return crc32c_sse42_u64(data, init_val);
> +#endif
>  
>  	if (likely(crc32_alg & CRC32_SSE42))
>  		return crc32c_sse42_u64_mimic(data, init_val);

-- 
Sincerely,

Yerden Zhumabekov
State Technical Service
Astana, KZ

Re: [dpdk-dev] [PATCH 3/3 v2] librte_eal/common: Fix redeclaration of enumerator ‘REG_EAX’

[Qiu, Michael]

On 2015/3/5 22:39, Thomas Monjalon wrote:
> 2015-03-05 14:03, Qiu, Michael:
>> On 3/5/2015 9:54 PM, David Marchand wrote:
>>> On Thu, Mar 5, 2015 at 2:50 PM, Michael Qiu <michael.qiu@intel.com
>>> <mailto:michael.qiu@intel.com>> wrote:
>>>
>>>     include/rte_cpuflags.h:154:2: error: redeclaration of enumerator
>>>     ‘REG_EAX’
>>>     In file included from /usr/include/signal.h:358:0,
>>>                      from /usr/include/sys/wait.h:30,
>>>                      from /root/dpdk/app/test/test_mp_secondary.c:50:
>>>     /usr/include/sys/ucontext.h:180:3: note: previous definition of
>>>     ‘REG_EAX’ was here
>>>
>>>     In i686, from REG_EAX to REG_EDX are all defined in
>>>             /usr/include/sys/ucontext.h
>>>
>>>     Rename to CPU_REG_EAX to avoid this issue.
>>>
>>>     Signed-off-by: Michael Qou <michael.qiu@intel.com
>>>     <mailto:michael.qiu@intel.com>>
>>>
>>>
>>> NAK.
>>>
>> I have answered in you last thread, please check the mail.
>>
>> Yes, but for some reason, it was not include, see /usr/include/signal.h:358
>>
>> # include <bits/sigstack.h>
>> # if defined __USE_XOPEN || defined __USE_XOPEN2K8
>> /* This will define `ucontext_t' and `mcontext_t'.  */
>> #  include <sys/ucontext.h>
>> # endif
>>
>> So only if __USE_XOPEN or __USE_XOPEN2K8 been defined will include 
>> <sys/ucontext.h>
> So try to define USE_XOPEN.
>
>> Why NAK?
> Because it seems you didn't really try to include system headers.

See below(ucontext.h:25):
#ifdef __x86_64__
...
#ifdef __USE_GNU
enmu{
    ...
  REG_RBX,
# define REG_RBX        REG_RBX
  REG_RDX,
# define REG_RDX        REG_RDX
  REG_RAX,
# define REG_RAX        REG_RAX
  REG_RCX,
# define REG_RCX        REG_RCX
...
};
#endif
...
#else /* !__x86_64__ */
...
#ifdef __USE_GNU
enmu{
...
  REG_EBX,
# define REG_EBX        REG_EBX
  REG_EDX,
# define REG_EDX        REG_EDX
  REG_ECX,
# define REG_ECX        REG_ECX
  REG_EAX,
# define REG_EAX        REG_EAX
...
};
#endif
...
#endif /* !__x86_64__ */


For none x86_64 platform will be defined as REG_E*X, but x86_64 will be
REG_R*X.

This is why only happens in i686 platform.

Does this clear?

Thanks,
Michael
> We must avoid redefine existing symbols. That's why this bug happens.
> Michael, thanks for trying to fix this issue. It's appreciated even if
> the first solution is refused.
>
>

Re: [dpdk-dev] [PATCH 1/3] librte_hash: Fix unsupported instruction `crc32' in i686 platform

[Qiu, Michael]

On 2015/3/6 0:12, Yerden Zhumabekov wrote:
> Hi Michael,
>
> Thanks for this patch, in fact I didn't try to compile it on i686 when
> developing original software fallback for CRC32.
>
> I think if we want to make code compilable as wide as possible, we
> should compile out all SSE4.2 instructions. As to the patch, we may
> compile out 'crc32l' instruction emitting code if the arch is not x86.
> This concerns two functions: crc32c_sse42_u32() and
> crc32c_sse42_u64_mimic().

OK, I will add the check for crc32l, make it only works for x86

Thanks,
Michael
> The compile check might be something like this:
>
> #if defined(RTE_ARCH_I686) || defined(RTE_ARCH_X86_64)
> #endif
>
> Otherwise, the patch looks good.
>
> 05.03.2015 19:15, Michael Qiu пишет:
>> CC rte_hash.o
>> Error: unsupported instruction `crc32'
>>
>> The root cause is that i686 platform does not support 'crc32q'
>> Need make it only available in x86_64 platform
>>
>> Signed-off-by: Michael Qiu <michael.qiu@intel.com>
>> ---
>>  lib/librte_hash/rte_hash_crc.h | 4 ++++
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/lib/librte_hash/rte_hash_crc.h b/lib/librte_hash/rte_hash_crc.h
>> index d28bb2a..4e9546f 100644
>> --- a/lib/librte_hash/rte_hash_crc.h
>> +++ b/lib/librte_hash/rte_hash_crc.h
>> @@ -374,6 +374,7 @@ crc32c_sse42_u32(uint32_t data, uint32_t init_val)
>>  	return init_val;
>>  }
>>  
>> +#ifdef RTE_ARCH_X86_64
>>  static inline uint32_t
>>  crc32c_sse42_u64(uint64_t data, uint64_t init_val)
>>  {
>> @@ -383,6 +384,7 @@ crc32c_sse42_u64(uint64_t data, uint64_t init_val)
>>  			: [data] "rm" (data));
>>  	return init_val;
>>  }
>> +#endif
>>  
>>  static inline uint32_t
>>  crc32c_sse42_u64_mimic(uint64_t data, uint64_t init_val)
>> @@ -476,8 +478,10 @@ rte_hash_crc_4byte(uint32_t data, uint32_t init_val)
>>  static inline uint32_t
>>  rte_hash_crc_8byte(uint64_t data, uint32_t init_val)
>>  {
>> +#ifdef RTE_ARCH_X86_64
>>  	if (likely(crc32_alg == CRC32_SSE42_x64))
>>  		return crc32c_sse42_u64(data, init_val);
>> +#endif
>>  
>>  	if (likely(crc32_alg & CRC32_SSE42))
>>  		return crc32c_sse42_u64_mimic(data, init_val);

[dpdk-dev] [PATCH 1/3 v2] librte_hash: Fix unsupported instruction `crc32' in i686 platform

[Michael Qiu]

CC rte_hash.o
Error: unsupported instruction `crc32'

The root cause is that i686 platform does not support 'crc32q'
Need make it only available in x86_64 platform

Signed-off-by: Michael Qiu <michael.qiu@intel.com>
---
v2 --> v1:
         Make crc32 instruction only works in X86 platform
 lib/librte_hash/rte_hash_crc.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/lib/librte_hash/rte_hash_crc.h b/lib/librte_hash/rte_hash_crc.h
index d28bb2a..c0a789e 100644
--- a/lib/librte_hash/rte_hash_crc.h
+++ b/lib/librte_hash/rte_hash_crc.h
@@ -364,6 +364,7 @@ crc32c_2words(uint64_t data, uint32_t init_val)
 	return crc;
 }
 
+#if defined RTE_ARCH_I686 || defined RTE_ARCH_X86_64
 static inline uint32_t
 crc32c_sse42_u32(uint32_t data, uint32_t init_val)
 {
@@ -373,7 +374,9 @@ crc32c_sse42_u32(uint32_t data, uint32_t init_val)
 			: [data] "rm" (data));
 	return init_val;
 }
+#endif
 
+#ifdef RTE_ARCH_X86_64
 static inline uint32_t
 crc32c_sse42_u64(uint64_t data, uint64_t init_val)
 {
@@ -383,7 +386,9 @@ crc32c_sse42_u64(uint64_t data, uint64_t init_val)
 			: [data] "rm" (data));
 	return init_val;
 }
+#endif
 
+#if defined RTE_ARCH_I686 || defined RTE_ARCH_X86_64
 static inline uint32_t
 crc32c_sse42_u64_mimic(uint64_t data, uint64_t init_val)
 {
@@ -397,6 +402,7 @@ crc32c_sse42_u64_mimic(uint64_t data, uint64_t init_val)
 	init_val = crc32c_sse42_u32(d.u32[1], init_val);
 	return init_val;
 }
+#endif
 
 #define CRC32_SW            (1U << 0)
 #define CRC32_SSE42         (1U << 1)
@@ -455,8 +461,10 @@ rte_hash_crc_init_alg(void)
 static inline uint32_t
 rte_hash_crc_4byte(uint32_t data, uint32_t init_val)
 {
+#if defined RTE_ARCH_I686 || defined RTE_ARCH_X86_64
 	if (likely(crc32_alg & CRC32_SSE42))
 		return crc32c_sse42_u32(data, init_val);
+#endif
 
 	return crc32c_1word(data, init_val);
 }
@@ -476,11 +484,15 @@ rte_hash_crc_4byte(uint32_t data, uint32_t init_val)
 static inline uint32_t
 rte_hash_crc_8byte(uint64_t data, uint32_t init_val)
 {
+#ifdef RTE_ARCH_X86_64
 	if (likely(crc32_alg == CRC32_SSE42_x64))
 		return crc32c_sse42_u64(data, init_val);
+#endif
 
+#if defined RTE_ARCH_I686 || defined RTE_ARCH_X86_64
 	if (likely(crc32_alg & CRC32_SSE42))
 		return crc32c_sse42_u64_mimic(data, init_val);
+#endif
 
 	return crc32c_2words(data, init_val);
 }
-- 
1.9.3

Re: [dpdk-dev] [PATCH 1/3 v2] librte_hash: Fix unsupported instruction `crc32' in i686 platform

[Yerden Zhumabekov]

Acked-by: Yerden Zhumabekov <yerden.zhumabekov@sts.kz>

05.03.2015 22:55, Michael Qiu пишет:
> CC rte_hash.o
> Error: unsupported instruction `crc32'
>
> The root cause is that i686 platform does not support 'crc32q'
> Need make it only available in x86_64 platform
>
> Signed-off-by: Michael Qiu <michael.qiu@intel.com>
> ---
> v2 --> v1:
>          Make crc32 instruction only works in X86 platform
>  lib/librte_hash/rte_hash_crc.h | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>
> diff --git a/lib/librte_hash/rte_hash_crc.h b/lib/librte_hash/rte_hash_crc.h
> index d28bb2a..c0a789e 100644
> --- a/lib/librte_hash/rte_hash_crc.h
> +++ b/lib/librte_hash/rte_hash_crc.h
> @@ -364,6 +364,7 @@ crc32c_2words(uint64_t data, uint32_t init_val)
>  	return crc;
>  }
>  
> +#if defined RTE_ARCH_I686 || defined RTE_ARCH_X86_64
>  static inline uint32_t
>  crc32c_sse42_u32(uint32_t data, uint32_t init_val)
>  {
> @@ -373,7 +374,9 @@ crc32c_sse42_u32(uint32_t data, uint32_t init_val)
>  			: [data] "rm" (data));
>  	return init_val;
>  }
> +#endif
>  
> +#ifdef RTE_ARCH_X86_64
>  static inline uint32_t
>  crc32c_sse42_u64(uint64_t data, uint64_t init_val)
>  {
> @@ -383,7 +386,9 @@ crc32c_sse42_u64(uint64_t data, uint64_t init_val)
>  			: [data] "rm" (data));
>  	return init_val;
>  }
> +#endif
>  
> +#if defined RTE_ARCH_I686 || defined RTE_ARCH_X86_64
>  static inline uint32_t
>  crc32c_sse42_u64_mimic(uint64_t data, uint64_t init_val)
>  {
> @@ -397,6 +402,7 @@ crc32c_sse42_u64_mimic(uint64_t data, uint64_t init_val)
>  	init_val = crc32c_sse42_u32(d.u32[1], init_val);
>  	return init_val;
>  }
> +#endif
>  
>  #define CRC32_SW            (1U << 0)
>  #define CRC32_SSE42         (1U << 1)
> @@ -455,8 +461,10 @@ rte_hash_crc_init_alg(void)
>  static inline uint32_t
>  rte_hash_crc_4byte(uint32_t data, uint32_t init_val)
>  {
> +#if defined RTE_ARCH_I686 || defined RTE_ARCH_X86_64
>  	if (likely(crc32_alg & CRC32_SSE42))
>  		return crc32c_sse42_u32(data, init_val);
> +#endif
>  
>  	return crc32c_1word(data, init_val);
>  }
> @@ -476,11 +484,15 @@ rte_hash_crc_4byte(uint32_t data, uint32_t init_val)
>  static inline uint32_t
>  rte_hash_crc_8byte(uint64_t data, uint32_t init_val)
>  {
> +#ifdef RTE_ARCH_X86_64
>  	if (likely(crc32_alg == CRC32_SSE42_x64))
>  		return crc32c_sse42_u64(data, init_val);
> +#endif
>  
> +#if defined RTE_ARCH_I686 || defined RTE_ARCH_X86_64
>  	if (likely(crc32_alg & CRC32_SSE42))
>  		return crc32c_sse42_u64_mimic(data, init_val);
> +#endif
>  
>  	return crc32c_2words(data, init_val);
>  }

-- 
Sincerely,

Yerden Zhumabekov
State Technical Service
Astana, KZ

Re: [dpdk-dev] [PATCH 1/3 v2] librte_hash: Fix unsupported instruction `crc32' in i686 platform

[Thomas Monjalon]

2015-03-06 00:55, Michael Qiu:
> CC rte_hash.o
> Error: unsupported instruction `crc32'
> 
> The root cause is that i686 platform does not support 'crc32q'
> Need make it only available in x86_64 platform
> 
> Signed-off-by: Michael Qiu <michael.qiu@intel.com>
> ---
> v2 --> v1:
>          Make crc32 instruction only works in X86 platform
>  lib/librte_hash/rte_hash_crc.h | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/lib/librte_hash/rte_hash_crc.h b/lib/librte_hash/rte_hash_crc.h
> index d28bb2a..c0a789e 100644
> --- a/lib/librte_hash/rte_hash_crc.h
> +++ b/lib/librte_hash/rte_hash_crc.h
> @@ -364,6 +364,7 @@ crc32c_2words(uint64_t data, uint32_t init_val)
>  	return crc;
>  }
>  
> +#if defined RTE_ARCH_I686 || defined RTE_ARCH_X86_64
>  static inline uint32_t
>  crc32c_sse42_u32(uint32_t data, uint32_t init_val)
>  {
> @@ -373,7 +374,9 @@ crc32c_sse42_u32(uint32_t data, uint32_t init_val)
>  			: [data] "rm" (data));
>  	return init_val;
>  }
> +#endif

Wouldn't it be more elegant to define a stub which returns 0 in #else
in order to remove #ifdef below?
Not sure, matter of taste.

[...]
> @@ -455,8 +461,10 @@ rte_hash_crc_init_alg(void)
>  static inline uint32_t
>  rte_hash_crc_4byte(uint32_t data, uint32_t init_val)
>  {
> +#if defined RTE_ARCH_I686 || defined RTE_ARCH_X86_64
>  	if (likely(crc32_alg & CRC32_SSE42))
>  		return crc32c_sse42_u32(data, init_val);
> +#endif
>  
>  	return crc32c_1word(data, init_val);
>  }
> @@ -476,11 +484,15 @@ rte_hash_crc_4byte(uint32_t data, uint32_t init_val)
>  static inline uint32_t
>  rte_hash_crc_8byte(uint64_t data, uint32_t init_val)
>  {
> +#ifdef RTE_ARCH_X86_64
>  	if (likely(crc32_alg == CRC32_SSE42_x64))
>  		return crc32c_sse42_u64(data, init_val);
> +#endif
>  
> +#if defined RTE_ARCH_I686 || defined RTE_ARCH_X86_64
>  	if (likely(crc32_alg & CRC32_SSE42))
>  		return crc32c_sse42_u64_mimic(data, init_val);
> +#endif
>  
>  	return crc32c_2words(data, init_val);
>  }
> 

Re: [dpdk-dev] [PATCH 2/3 v2] app/test: Fix size_t printf format issue

[Thomas Monjalon]

2015-03-05 22:00, Michael Qiu:
> test_hash.c: In function ‘test_crc32_hash_alg_equiv’:
> error: format ‘%lu’ expects argument of type ‘long unsigned int’,
> but argument 2 has type ‘size_t’ [-Werror=format]
> 
> According to C99, for size_t type should use format "%zu"
> 
> Signed-off-by: Michael Qiu <michael.qiu@intel.com>

You forgot to add the previous acknowledgement from Bruce.

Re: [dpdk-dev] [PATCH 3/3 v2] librte_eal/common: Fix redeclaration of enumerator ‘REG_EAX’

[Thomas Monjalon]

2015-03-05 16:31, Qiu, Michael:
> On 2015/3/5 22:39, Thomas Monjalon wrote:
> > 2015-03-05 14:03, Qiu, Michael:
> >> On 3/5/2015 9:54 PM, David Marchand wrote:
> >>> On Thu, Mar 5, 2015 at 2:50 PM, Michael Qiu <michael.qiu@intel.com
> >>> <mailto:michael.qiu@intel.com>> wrote:
> >>>
> >>>     include/rte_cpuflags.h:154:2: error: redeclaration of enumerator
> >>>     ‘REG_EAX’
> >>>     In file included from /usr/include/signal.h:358:0,
> >>>                      from /usr/include/sys/wait.h:30,
> >>>                      from /root/dpdk/app/test/test_mp_secondary.c:50:
> >>>     /usr/include/sys/ucontext.h:180:3: note: previous definition of
> >>>     ‘REG_EAX’ was here
> >>>
> >>>     In i686, from REG_EAX to REG_EDX are all defined in
> >>>             /usr/include/sys/ucontext.h
> >>>
> >>>     Rename to CPU_REG_EAX to avoid this issue.
> >>>
> >>>     Signed-off-by: Michael Qou <michael.qiu@intel.com
> >>>     <mailto:michael.qiu@intel.com>>
> >>>
> >>>
> >>> NAK.
> >>>
> >> I have answered in you last thread, please check the mail.
> >>
> >> Yes, but for some reason, it was not include, see /usr/include/signal.h:358
> >>
> >> # include <bits/sigstack.h>
> >> # if defined __USE_XOPEN || defined __USE_XOPEN2K8
> >> /* This will define `ucontext_t' and `mcontext_t'.  */
> >> #  include <sys/ucontext.h>
> >> # endif
> >>
> >> So only if __USE_XOPEN or __USE_XOPEN2K8 been defined will include 
> >> <sys/ucontext.h>
> > So try to define USE_XOPEN.
> >
> >> Why NAK?
> > Because it seems you didn't really try to include system headers.
> 
> See below(ucontext.h:25):
> #ifdef __x86_64__
> ...
> #ifdef __USE_GNU
> enmu{
>     ...
>   REG_RBX,
> # define REG_RBX        REG_RBX
>   REG_RDX,
> # define REG_RDX        REG_RDX
>   REG_RAX,
> # define REG_RAX        REG_RAX
>   REG_RCX,
> # define REG_RCX        REG_RCX
> ...
> };
> #endif
> ...
> #else /* !__x86_64__ */
> ...
> #ifdef __USE_GNU
> enmu{
> ...
>   REG_EBX,
> # define REG_EBX        REG_EBX
>   REG_EDX,
> # define REG_EDX        REG_EDX
>   REG_ECX,
> # define REG_ECX        REG_ECX
>   REG_EAX,
> # define REG_EAX        REG_EAX
> ...
> };
> #endif
> ...
> #endif /* !__x86_64__ */
> 
> 
> For none x86_64 platform will be defined as REG_E*X, but x86_64 will be
> REG_R*X.
> 
> This is why only happens in i686 platform.
> 
> Does this clear?

OK thanks.
So it is not possible to use this system header.
It seems your patch is a good approach.

Re: [dpdk-dev] [PATCH 1/3 v2] librte_hash: Fix unsupported instruction `crc32' in i686 platform

[Qiu, Michael]

On 3/6/2015 1:11 AM, Thomas Monjalon wrote:
> 2015-03-06 00:55, Michael Qiu:
>> CC rte_hash.o
>> Error: unsupported instruction `crc32'
>>
>> The root cause is that i686 platform does not support 'crc32q'
>> Need make it only available in x86_64 platform
>>
>> Signed-off-by: Michael Qiu <michael.qiu@intel.com>
>> ---
>> v2 --> v1:
>>          Make crc32 instruction only works in X86 platform
>>  lib/librte_hash/rte_hash_crc.h | 12 ++++++++++++
>>  1 file changed, 12 insertions(+)
>>
>> diff --git a/lib/librte_hash/rte_hash_crc.h b/lib/librte_hash/rte_hash_crc.h
>> index d28bb2a..c0a789e 100644
>> --- a/lib/librte_hash/rte_hash_crc.h
>> +++ b/lib/librte_hash/rte_hash_crc.h
>> @@ -364,6 +364,7 @@ crc32c_2words(uint64_t data, uint32_t init_val)
>>  	return crc;
>>  }
>>  
>> +#if defined RTE_ARCH_I686 || defined RTE_ARCH_X86_64
>>  static inline uint32_t
>>  crc32c_sse42_u32(uint32_t data, uint32_t init_val)
>>  {
>> @@ -373,7 +374,9 @@ crc32c_sse42_u32(uint32_t data, uint32_t init_val)
>>  			: [data] "rm" (data));
>>  	return init_val;
>>  }
>> +#endif
> Wouldn't it be more elegant to define a stub which returns 0 in #else
> in order to remove #ifdef below?
> Not sure, matter of taste.

It may be not a good idea, see rte_hash_crc_8byte(), if no crc32
support, it will use crc32c_2words(), if we define a stub which returns
0 in #else, then we need always check the return value whether it is
none-zero otherwise need fallback.

Thanks,
Michael
> [...]
>> @@ -455,8 +461,10 @@ rte_hash_crc_init_alg(void)
>>  static inline uint32_t
>>  rte_hash_crc_4byte(uint32_t data, uint32_t init_val)
>>  {
>> +#if defined RTE_ARCH_I686 || defined RTE_ARCH_X86_64
>>  	if (likely(crc32_alg & CRC32_SSE42))
>>  		return crc32c_sse42_u32(data, init_val);
>> +#endif
>>  
>>  	return crc32c_1word(data, init_val);
>>  }
>> @@ -476,11 +484,15 @@ rte_hash_crc_4byte(uint32_t data, uint32_t init_val)
>>  static inline uint32_t
>>  rte_hash_crc_8byte(uint64_t data, uint32_t init_val)
>>  {
>> +#ifdef RTE_ARCH_X86_64
>>  	if (likely(crc32_alg == CRC32_SSE42_x64))
>>  		return crc32c_sse42_u64(data, init_val);
>> +#endif
>>  
>> +#if defined RTE_ARCH_I686 || defined RTE_ARCH_X86_64
>>  	if (likely(crc32_alg & CRC32_SSE42))
>>  		return crc32c_sse42_u64_mimic(data, init_val);
>> +#endif
>>  
>>  	return crc32c_2words(data, init_val);
>>  }
>>
>
>

Re: [dpdk-dev] [PATCH 2/3 v2] app/test: Fix size_t printf format issue

[Qiu, Michael]

On 3/6/2015 1:28 AM, Thomas Monjalon wrote:
> 2015-03-05 22:00, Michael Qiu:
>> test_hash.c: In function ‘test_crc32_hash_alg_equiv’:
>> error: format ‘%lu’ expects argument of type ‘long unsigned int’,
>> but argument 2 has type ‘size_t’ [-Werror=format]
>>
>> According to C99, for size_t type should use format "%zu"
>>
>> Signed-off-by: Michael Qiu <michael.qiu@intel.com>
> You forgot to add the previous acknowledgement from Bruce.
>
>
OK, I will send out v3 to add previous acknowledgement from Bruce.

Thanks,
Michael

[dpdk-dev] [PATCH 2/3 v3] app/test: Fix size_t printf format issue

[Michael Qiu]

test_hash.c: In function ‘test_crc32_hash_alg_equiv’:
error: format ‘%lu’ expects argument of type ‘long unsigned int’,
but argument 2 has type ‘size_t’ [-Werror=format]

According to C99, for size_t type should use format "%zu"

Signed-off-by: Michael Qiu <michael.qiu@intel.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
---
v3 --> v2:
	add acked-by field 
v2 --> v1:
	typo fix of "format" in commit log and title

 app/test/test_hash.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/app/test/test_hash.c b/app/test/test_hash.c
index 653dd86..c489b8b 100644
--- a/app/test/test_hash.c
+++ b/app/test/test_hash.c
@@ -226,7 +226,7 @@ test_crc32_hash_alg_equiv(void)
 	if (i == CRC32_ITERATIONS)
 		return 0;
 
-	printf("Failed test data (hex, %lu bytes total):\n", data_len);
+	printf("Failed test data (hex, %zu bytes total):\n", data_len);
 	for (j = 0; j < data_len; j++)
 		printf("%02X%c", ((uint8_t *)data64)[j],
 				((j+1) % 16 == 0 || j == data_len - 1) ? '\n' : ' ');
-- 
1.9.3

Re: [dpdk-dev] [PATCH 3/3 v3] librte_eal/common: Fix redeclaration of enumerator ‘REG_EAX’

[David Marchand]

On Thu, Mar 5, 2015 at 2:57 PM, Michael Qiu <michael.qiu@intel.com> wrote:

> include/rte_cpuflags.h:154:2: error: redeclaration of enumerator ‘REG_EAX’
> In file included from /usr/include/signal.h:358:0,
>                  from /usr/include/sys/wait.h:30,
>                  from /root/dpdk/app/test/test_mp_secondary.c:50:
> /usr/include/sys/ucontext.h:180:3: note: previous definition of ‘REG_EAX’
> was here
>
> In i686, from REG_EAX to REG_EDX are all defined in
>         /usr/include/sys/ucontext.h
>
> Rename to CPU_REG_EAX to avoid this issue.
>

Thomas,
- title must be fixed
- commit log must be fixed :CPU_REG_EAX -> RTE_REG_EAX

There is still some ambiguity in these macros names to me, but this is the
quickest fix, so :
Acked-by: David Marchand <david.marchand@6wind.com>

-- 
David Marchand


>
> Signed-off-by: Michael Qiu <michael.qiu@intel.com>
> ---
> v3 --> v2:
>         Fix signed-off-by field
> v2 --> v1:
>         rename CPU_REG_EAX to RTE_REG_EAX
>
>  .../common/include/arch/x86/rte_cpuflags.h         | 210
> ++++++++++-----------
>  1 file changed, 105 insertions(+), 105 deletions(-)
>
> diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
> b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
> index a58dd7b..dd56553 100644
> --- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
> +++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
> @@ -151,104 +151,104 @@ enum rte_cpu_flag_t {
>  };
>
>  enum cpu_register_t {
> -       REG_EAX = 0,
> -       REG_EBX,
> -       REG_ECX,
> -       REG_EDX,
> +       RTE_REG_EAX = 0,
> +       RTE_REG_EBX,
> +       RTE_REG_ECX,
> +       RTE_REG_EDX,
>  };
>
>  static const struct feature_entry cpu_feature_table[] = {
> -       FEAT_DEF(SSE3, 0x00000001, 0, REG_ECX,  0)
> -       FEAT_DEF(PCLMULQDQ, 0x00000001, 0, REG_ECX,  1)
> -       FEAT_DEF(DTES64, 0x00000001, 0, REG_ECX,  2)
> -       FEAT_DEF(MONITOR, 0x00000001, 0, REG_ECX,  3)
> -       FEAT_DEF(DS_CPL, 0x00000001, 0, REG_ECX,  4)
> -       FEAT_DEF(VMX, 0x00000001, 0, REG_ECX,  5)
> -       FEAT_DEF(SMX, 0x00000001, 0, REG_ECX,  6)
> -       FEAT_DEF(EIST, 0x00000001, 0, REG_ECX,  7)
> -       FEAT_DEF(TM2, 0x00000001, 0, REG_ECX,  8)
> -       FEAT_DEF(SSSE3, 0x00000001, 0, REG_ECX,  9)
> -       FEAT_DEF(CNXT_ID, 0x00000001, 0, REG_ECX, 10)
> -       FEAT_DEF(FMA, 0x00000001, 0, REG_ECX, 12)
> -       FEAT_DEF(CMPXCHG16B, 0x00000001, 0, REG_ECX, 13)
> -       FEAT_DEF(XTPR, 0x00000001, 0, REG_ECX, 14)
> -       FEAT_DEF(PDCM, 0x00000001, 0, REG_ECX, 15)
> -       FEAT_DEF(PCID, 0x00000001, 0, REG_ECX, 17)
> -       FEAT_DEF(DCA, 0x00000001, 0, REG_ECX, 18)
> -       FEAT_DEF(SSE4_1, 0x00000001, 0, REG_ECX, 19)
> -       FEAT_DEF(SSE4_2, 0x00000001, 0, REG_ECX, 20)
> -       FEAT_DEF(X2APIC, 0x00000001, 0, REG_ECX, 21)
> -       FEAT_DEF(MOVBE, 0x00000001, 0, REG_ECX, 22)
> -       FEAT_DEF(POPCNT, 0x00000001, 0, REG_ECX, 23)
> -       FEAT_DEF(TSC_DEADLINE, 0x00000001, 0, REG_ECX, 24)
> -       FEAT_DEF(AES, 0x00000001, 0, REG_ECX, 25)
> -       FEAT_DEF(XSAVE, 0x00000001, 0, REG_ECX, 26)
> -       FEAT_DEF(OSXSAVE, 0x00000001, 0, REG_ECX, 27)
> -       FEAT_DEF(AVX, 0x00000001, 0, REG_ECX, 28)
> -       FEAT_DEF(F16C, 0x00000001, 0, REG_ECX, 29)
> -       FEAT_DEF(RDRAND, 0x00000001, 0, REG_ECX, 30)
> -
> -       FEAT_DEF(FPU, 0x00000001, 0, REG_EDX,  0)
> -       FEAT_DEF(VME, 0x00000001, 0, REG_EDX,  1)
> -       FEAT_DEF(DE, 0x00000001, 0, REG_EDX,  2)
> -       FEAT_DEF(PSE, 0x00000001, 0, REG_EDX,  3)
> -       FEAT_DEF(TSC, 0x00000001, 0, REG_EDX,  4)
> -       FEAT_DEF(MSR, 0x00000001, 0, REG_EDX,  5)
> -       FEAT_DEF(PAE, 0x00000001, 0, REG_EDX,  6)
> -       FEAT_DEF(MCE, 0x00000001, 0, REG_EDX,  7)
> -       FEAT_DEF(CX8, 0x00000001, 0, REG_EDX,  8)
> -       FEAT_DEF(APIC, 0x00000001, 0, REG_EDX,  9)
> -       FEAT_DEF(SEP, 0x00000001, 0, REG_EDX, 11)
> -       FEAT_DEF(MTRR, 0x00000001, 0, REG_EDX, 12)
> -       FEAT_DEF(PGE, 0x00000001, 0, REG_EDX, 13)
> -       FEAT_DEF(MCA, 0x00000001, 0, REG_EDX, 14)
> -       FEAT_DEF(CMOV, 0x00000001, 0, REG_EDX, 15)
> -       FEAT_DEF(PAT, 0x00000001, 0, REG_EDX, 16)
> -       FEAT_DEF(PSE36, 0x00000001, 0, REG_EDX, 17)
> -       FEAT_DEF(PSN, 0x00000001, 0, REG_EDX, 18)
> -       FEAT_DEF(CLFSH, 0x00000001, 0, REG_EDX, 19)
> -       FEAT_DEF(DS, 0x00000001, 0, REG_EDX, 21)
> -       FEAT_DEF(ACPI, 0x00000001, 0, REG_EDX, 22)
> -       FEAT_DEF(MMX, 0x00000001, 0, REG_EDX, 23)
> -       FEAT_DEF(FXSR, 0x00000001, 0, REG_EDX, 24)
> -       FEAT_DEF(SSE, 0x00000001, 0, REG_EDX, 25)
> -       FEAT_DEF(SSE2, 0x00000001, 0, REG_EDX, 26)
> -       FEAT_DEF(SS, 0x00000001, 0, REG_EDX, 27)
> -       FEAT_DEF(HTT, 0x00000001, 0, REG_EDX, 28)
> -       FEAT_DEF(TM, 0x00000001, 0, REG_EDX, 29)
> -       FEAT_DEF(PBE, 0x00000001, 0, REG_EDX, 31)
> -
> -       FEAT_DEF(DIGTEMP, 0x00000006, 0, REG_EAX,  0)
> -       FEAT_DEF(TRBOBST, 0x00000006, 0, REG_EAX,  1)
> -       FEAT_DEF(ARAT, 0x00000006, 0, REG_EAX,  2)
> -       FEAT_DEF(PLN, 0x00000006, 0, REG_EAX,  4)
> -       FEAT_DEF(ECMD, 0x00000006, 0, REG_EAX,  5)
> -       FEAT_DEF(PTM, 0x00000006, 0, REG_EAX,  6)
> -
> -       FEAT_DEF(MPERF_APERF_MSR, 0x00000006, 0, REG_ECX,  0)
> -       FEAT_DEF(ACNT2, 0x00000006, 0, REG_ECX,  1)
> -       FEAT_DEF(ENERGY_EFF, 0x00000006, 0, REG_ECX,  3)
> -
> -       FEAT_DEF(FSGSBASE, 0x00000007, 0, REG_EBX,  0)
> -       FEAT_DEF(BMI1, 0x00000007, 0, REG_EBX,  2)
> -       FEAT_DEF(HLE, 0x00000007, 0, REG_EBX,  4)
> -       FEAT_DEF(AVX2, 0x00000007, 0, REG_EBX,  5)
> -       FEAT_DEF(SMEP, 0x00000007, 0, REG_EBX,  6)
> -       FEAT_DEF(BMI2, 0x00000007, 0, REG_EBX,  7)
> -       FEAT_DEF(ERMS, 0x00000007, 0, REG_EBX,  8)
> -       FEAT_DEF(INVPCID, 0x00000007, 0, REG_EBX, 10)
> -       FEAT_DEF(RTM, 0x00000007, 0, REG_EBX, 11)
> -
> -       FEAT_DEF(LAHF_SAHF, 0x80000001, 0, REG_ECX,  0)
> -       FEAT_DEF(LZCNT, 0x80000001, 0, REG_ECX,  4)
> -
> -       FEAT_DEF(SYSCALL, 0x80000001, 0, REG_EDX, 11)
> -       FEAT_DEF(XD, 0x80000001, 0, REG_EDX, 20)
> -       FEAT_DEF(1GB_PG, 0x80000001, 0, REG_EDX, 26)
> -       FEAT_DEF(RDTSCP, 0x80000001, 0, REG_EDX, 27)
> -       FEAT_DEF(EM64T, 0x80000001, 0, REG_EDX, 29)
> -
> -       FEAT_DEF(INVTSC, 0x80000007, 0, REG_EDX,  8)
> +       FEAT_DEF(SSE3, 0x00000001, 0, RTE_REG_ECX,  0)
> +       FEAT_DEF(PCLMULQDQ, 0x00000001, 0, RTE_REG_ECX,  1)
> +       FEAT_DEF(DTES64, 0x00000001, 0, RTE_REG_ECX,  2)
> +       FEAT_DEF(MONITOR, 0x00000001, 0, RTE_REG_ECX,  3)
> +       FEAT_DEF(DS_CPL, 0x00000001, 0, RTE_REG_ECX,  4)
> +       FEAT_DEF(VMX, 0x00000001, 0, RTE_REG_ECX,  5)
> +       FEAT_DEF(SMX, 0x00000001, 0, RTE_REG_ECX,  6)
> +       FEAT_DEF(EIST, 0x00000001, 0, RTE_REG_ECX,  7)
> +       FEAT_DEF(TM2, 0x00000001, 0, RTE_REG_ECX,  8)
> +       FEAT_DEF(SSSE3, 0x00000001, 0, RTE_REG_ECX,  9)
> +       FEAT_DEF(CNXT_ID, 0x00000001, 0, RTE_REG_ECX, 10)
> +       FEAT_DEF(FMA, 0x00000001, 0, RTE_REG_ECX, 12)
> +       FEAT_DEF(CMPXCHG16B, 0x00000001, 0, RTE_REG_ECX, 13)
> +       FEAT_DEF(XTPR, 0x00000001, 0, RTE_REG_ECX, 14)
> +       FEAT_DEF(PDCM, 0x00000001, 0, RTE_REG_ECX, 15)
> +       FEAT_DEF(PCID, 0x00000001, 0, RTE_REG_ECX, 17)
> +       FEAT_DEF(DCA, 0x00000001, 0, RTE_REG_ECX, 18)
> +       FEAT_DEF(SSE4_1, 0x00000001, 0, RTE_REG_ECX, 19)
> +       FEAT_DEF(SSE4_2, 0x00000001, 0, RTE_REG_ECX, 20)
> +       FEAT_DEF(X2APIC, 0x00000001, 0, RTE_REG_ECX, 21)
> +       FEAT_DEF(MOVBE, 0x00000001, 0, RTE_REG_ECX, 22)
> +       FEAT_DEF(POPCNT, 0x00000001, 0, RTE_REG_ECX, 23)
> +       FEAT_DEF(TSC_DEADLINE, 0x00000001, 0, RTE_REG_ECX, 24)
> +       FEAT_DEF(AES, 0x00000001, 0, RTE_REG_ECX, 25)
> +       FEAT_DEF(XSAVE, 0x00000001, 0, RTE_REG_ECX, 26)
> +       FEAT_DEF(OSXSAVE, 0x00000001, 0, RTE_REG_ECX, 27)
> +       FEAT_DEF(AVX, 0x00000001, 0, RTE_REG_ECX, 28)
> +       FEAT_DEF(F16C, 0x00000001, 0, RTE_REG_ECX, 29)
> +       FEAT_DEF(RDRAND, 0x00000001, 0, RTE_REG_ECX, 30)
> +
> +       FEAT_DEF(FPU, 0x00000001, 0, RTE_REG_EDX,  0)
> +       FEAT_DEF(VME, 0x00000001, 0, RTE_REG_EDX,  1)
> +       FEAT_DEF(DE, 0x00000001, 0, RTE_REG_EDX,  2)
> +       FEAT_DEF(PSE, 0x00000001, 0, RTE_REG_EDX,  3)
> +       FEAT_DEF(TSC, 0x00000001, 0, RTE_REG_EDX,  4)
> +       FEAT_DEF(MSR, 0x00000001, 0, RTE_REG_EDX,  5)
> +       FEAT_DEF(PAE, 0x00000001, 0, RTE_REG_EDX,  6)
> +       FEAT_DEF(MCE, 0x00000001, 0, RTE_REG_EDX,  7)
> +       FEAT_DEF(CX8, 0x00000001, 0, RTE_REG_EDX,  8)
> +       FEAT_DEF(APIC, 0x00000001, 0, RTE_REG_EDX,  9)
> +       FEAT_DEF(SEP, 0x00000001, 0, RTE_REG_EDX, 11)
> +       FEAT_DEF(MTRR, 0x00000001, 0, RTE_REG_EDX, 12)
> +       FEAT_DEF(PGE, 0x00000001, 0, RTE_REG_EDX, 13)
> +       FEAT_DEF(MCA, 0x00000001, 0, RTE_REG_EDX, 14)
> +       FEAT_DEF(CMOV, 0x00000001, 0, RTE_REG_EDX, 15)
> +       FEAT_DEF(PAT, 0x00000001, 0, RTE_REG_EDX, 16)
> +       FEAT_DEF(PSE36, 0x00000001, 0, RTE_REG_EDX, 17)
> +       FEAT_DEF(PSN, 0x00000001, 0, RTE_REG_EDX, 18)
> +       FEAT_DEF(CLFSH, 0x00000001, 0, RTE_REG_EDX, 19)
> +       FEAT_DEF(DS, 0x00000001, 0, RTE_REG_EDX, 21)
> +       FEAT_DEF(ACPI, 0x00000001, 0, RTE_REG_EDX, 22)
> +       FEAT_DEF(MMX, 0x00000001, 0, RTE_REG_EDX, 23)
> +       FEAT_DEF(FXSR, 0x00000001, 0, RTE_REG_EDX, 24)
> +       FEAT_DEF(SSE, 0x00000001, 0, RTE_REG_EDX, 25)
> +       FEAT_DEF(SSE2, 0x00000001, 0, RTE_REG_EDX, 26)
> +       FEAT_DEF(SS, 0x00000001, 0, RTE_REG_EDX, 27)
> +       FEAT_DEF(HTT, 0x00000001, 0, RTE_REG_EDX, 28)
> +       FEAT_DEF(TM, 0x00000001, 0, RTE_REG_EDX, 29)
> +       FEAT_DEF(PBE, 0x00000001, 0, RTE_REG_EDX, 31)
> +
> +       FEAT_DEF(DIGTEMP, 0x00000006, 0, RTE_REG_EAX,  0)
> +       FEAT_DEF(TRBOBST, 0x00000006, 0, RTE_REG_EAX,  1)
> +       FEAT_DEF(ARAT, 0x00000006, 0, RTE_REG_EAX,  2)
> +       FEAT_DEF(PLN, 0x00000006, 0, RTE_REG_EAX,  4)
> +       FEAT_DEF(ECMD, 0x00000006, 0, RTE_REG_EAX,  5)
> +       FEAT_DEF(PTM, 0x00000006, 0, RTE_REG_EAX,  6)
> +
> +       FEAT_DEF(MPERF_APERF_MSR, 0x00000006, 0, RTE_REG_ECX,  0)
> +       FEAT_DEF(ACNT2, 0x00000006, 0, RTE_REG_ECX,  1)
> +       FEAT_DEF(ENERGY_EFF, 0x00000006, 0, RTE_REG_ECX,  3)
> +
> +       FEAT_DEF(FSGSBASE, 0x00000007, 0, RTE_REG_EBX,  0)
> +       FEAT_DEF(BMI1, 0x00000007, 0, RTE_REG_EBX,  2)
> +       FEAT_DEF(HLE, 0x00000007, 0, RTE_REG_EBX,  4)
> +       FEAT_DEF(AVX2, 0x00000007, 0, RTE_REG_EBX,  5)
> +       FEAT_DEF(SMEP, 0x00000007, 0, RTE_REG_EBX,  6)
> +       FEAT_DEF(BMI2, 0x00000007, 0, RTE_REG_EBX,  7)
> +       FEAT_DEF(ERMS, 0x00000007, 0, RTE_REG_EBX,  8)
> +       FEAT_DEF(INVPCID, 0x00000007, 0, RTE_REG_EBX, 10)
> +       FEAT_DEF(RTM, 0x00000007, 0, RTE_REG_EBX, 11)
> +
> +       FEAT_DEF(LAHF_SAHF, 0x80000001, 0, RTE_REG_ECX,  0)
> +       FEAT_DEF(LZCNT, 0x80000001, 0, RTE_REG_ECX,  4)
> +
> +       FEAT_DEF(SYSCALL, 0x80000001, 0, RTE_REG_EDX, 11)
> +       FEAT_DEF(XD, 0x80000001, 0, RTE_REG_EDX, 20)
> +       FEAT_DEF(1GB_PG, 0x80000001, 0, RTE_REG_EDX, 26)
> +       FEAT_DEF(RDTSCP, 0x80000001, 0, RTE_REG_EDX, 27)
> +       FEAT_DEF(EM64T, 0x80000001, 0, RTE_REG_EDX, 29)
> +
> +       FEAT_DEF(INVTSC, 0x80000007, 0, RTE_REG_EDX,  8)
>  };
>
>  static inline void
> @@ -257,18 +257,18 @@ rte_cpu_get_features(uint32_t leaf, uint32_t
> subleaf, cpuid_registers_t out)
>  #if defined(__i386__) && defined(__PIC__)
>      /* %ebx is a forbidden register if we compile with -fPIC or -fPIE */
>      asm volatile("movl %%ebx,%0 ; cpuid ; xchgl %%ebx,%0"
> -                : "=r" (out[REG_EBX]),
> -                  "=a" (out[REG_EAX]),
> -                  "=c" (out[REG_ECX]),
> -                  "=d" (out[REG_EDX])
> +                : "=r" (out[RTE_REG_EBX]),
> +                  "=a" (out[RTE_REG_EAX]),
> +                  "=c" (out[RTE_REG_ECX]),
> +                  "=d" (out[RTE_REG_EDX])
>                  : "a" (leaf), "c" (subleaf));
>  #else
>
>      asm volatile("cpuid"
> -                : "=a" (out[REG_EAX]),
> -                  "=b" (out[REG_EBX]),
> -                  "=c" (out[REG_ECX]),
> -                  "=d" (out[REG_EDX])
> +                : "=a" (out[RTE_REG_EAX]),
> +                  "=b" (out[RTE_REG_EBX]),
> +                  "=c" (out[RTE_REG_ECX]),
> +                  "=d" (out[RTE_REG_EDX])
>                  : "a" (leaf), "c" (subleaf));
>
>  #endif
> @@ -292,8 +292,8 @@ rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
>                 return -EFAULT;
>
>         rte_cpu_get_features(feat->leaf & 0xffff0000, 0, regs);
> -       if (((regs[REG_EAX] ^ feat->leaf) & 0xffff0000) ||
> -             regs[REG_EAX] < feat->leaf)
> +       if (((regs[RTE_REG_EAX] ^ feat->leaf) & 0xffff0000) ||
> +             regs[RTE_REG_EAX] < feat->leaf)
>                 return 0;
>
>         /* get the cpuid leaf containing the desired feature */
> --
> 1.9.3
>
>

Re: [dpdk-dev] [PATCH 1/3 v2] librte_hash: Fix unsupported instruction `crc32' in i686 platform

[Thomas Monjalon]

2015-03-06 01:39, Qiu, Michael:
> On 3/6/2015 1:11 AM, Thomas Monjalon wrote:
> > 2015-03-06 00:55, Michael Qiu:
> >> CC rte_hash.o
> >> Error: unsupported instruction `crc32'
> >>
> >> The root cause is that i686 platform does not support 'crc32q'
> >> Need make it only available in x86_64 platform
> >>
> >> Signed-off-by: Michael Qiu <michael.qiu@intel.com>
> >> ---
> >> v2 --> v1:
> >>          Make crc32 instruction only works in X86 platform
> >>  lib/librte_hash/rte_hash_crc.h | 12 ++++++++++++
> >>  1 file changed, 12 insertions(+)
> >>
> >> diff --git a/lib/librte_hash/rte_hash_crc.h b/lib/librte_hash/rte_hash_crc.h
> >> index d28bb2a..c0a789e 100644
> >> --- a/lib/librte_hash/rte_hash_crc.h
> >> +++ b/lib/librte_hash/rte_hash_crc.h
> >> @@ -364,6 +364,7 @@ crc32c_2words(uint64_t data, uint32_t init_val)
> >>  	return crc;
> >>  }
> >>  
> >> +#if defined RTE_ARCH_I686 || defined RTE_ARCH_X86_64
> >>  static inline uint32_t
> >>  crc32c_sse42_u32(uint32_t data, uint32_t init_val)
> >>  {
> >> @@ -373,7 +374,9 @@ crc32c_sse42_u32(uint32_t data, uint32_t init_val)
> >>  			: [data] "rm" (data));
> >>  	return init_val;
> >>  }
> >> +#endif
> > 
> > Wouldn't it be more elegant to define a stub which returns 0 in #else
> > in order to remove #ifdef below?
> > Not sure, matter of taste.
> 
> It may be not a good idea, see rte_hash_crc_8byte(), if no crc32
> support, it will use crc32c_2words(), if we define a stub which returns
> 0 in #else, then we need always check the return value whether it is
> none-zero otherwise need fallback.

I don't think so.
The stub won't never been called because they are protected by the cpuflag
condition.

[dpdk-dev] [PATCH 1/3 v3] librte_hash: Fix unsupported instruction `crc32' in i686 platform

[Michael Qiu]

CC rte_hash.o
Error: unsupported instruction `crc32'

The root cause is that i686 platform does not support 'crc32q'
Need make it only available in x86_64 platform

Signed-off-by: Michael Qiu <michael.qiu@intel.com>
Acked-by: Yerden Zhumabekov <yerden.zhumabekov@sts.kz>
---
v3 --> v2:
	Add sub function for #else which returns 0
v2 --> v1:
         Make crc32 instruction only works in X86 platform

 lib/librte_hash/rte_hash_crc.h | 46 +++++++++++++++++++++++++++++++++---------
 1 file changed, 36 insertions(+), 10 deletions(-)

diff --git a/lib/librte_hash/rte_hash_crc.h b/lib/librte_hash/rte_hash_crc.h
index d28bb2a..f1dbded 100644
--- a/lib/librte_hash/rte_hash_crc.h
+++ b/lib/librte_hash/rte_hash_crc.h
@@ -47,6 +47,7 @@ extern "C" {
 #include <stdint.h>
 #include <rte_cpuflags.h>
 #include <rte_branch_prediction.h>
+#include <rte_common.h>
 
 /* Lookup tables for software implementation of CRC32C */
 static const uint32_t crc32c_tables[8][256] = {{
@@ -364,6 +365,7 @@ crc32c_2words(uint64_t data, uint32_t init_val)
 	return crc;
 }
 
+#if defined(RTE_ARCH_I686) || defined(RTE_ARCH_X86_64)
 static inline uint32_t
 crc32c_sse42_u32(uint32_t data, uint32_t init_val)
 {
@@ -375,16 +377,6 @@ crc32c_sse42_u32(uint32_t data, uint32_t init_val)
 }
 
 static inline uint32_t
-crc32c_sse42_u64(uint64_t data, uint64_t init_val)
-{
-	__asm__ volatile(
-			"crc32q %[data], %[init_val];"
-			: [init_val] "+r" (init_val)
-			: [data] "rm" (data));
-	return init_val;
-}
-
-static inline uint32_t
 crc32c_sse42_u64_mimic(uint64_t data, uint64_t init_val)
 {
 	union {
@@ -397,6 +389,40 @@ crc32c_sse42_u64_mimic(uint64_t data, uint64_t init_val)
 	init_val = crc32c_sse42_u32(d.u32[1], init_val);
 	return init_val;
 }
+#else
+static inline uint32_t
+crc32c_sse42_u32(__rte_unused uint32_t data,
+		 __rte_unused uint32_t init_val)
+{
+	return 0;
+}
+
+static inline uint32_t
+crc32c_sse42_u64_mimic(__rte_unused uint32_t data,
+		       __rte_unused uint32_t init_val)
+{
+	return 0;
+}
+#endif
+
+#ifdef RTE_ARCH_X86_64
+static inline uint32_t
+crc32c_sse42_u64(uint64_t data, uint64_t init_val)
+{
+	__asm__ volatile(
+			"crc32q %[data], %[init_val];"
+			: [init_val] "+r" (init_val)
+			: [data] "rm" (data));
+	return init_val;
+}
+#else
+static inline uint32_t
+crc32c_sse42_u64(__rte_unused uint64_t data,
+		 __rte_unused uint64_t init_val)
+{
+	return 0;
+}
+#endif
 
 #define CRC32_SW            (1U << 0)
 #define CRC32_SSE42         (1U << 1)
-- 
1.9.3

Re: [dpdk-dev] [PATCH 0/3] dpdk2.0-rc1 build error fix

[Thomas Monjalon]

2015-03-05 21:15, Michael Qiu:
> This patch set is to fix dpdk2.0-rc1 compile error.
> 
> Michael Qiu (3):
>   librte_hash: Fix unsupported instruction `crc32' in i686 platform
>   app/test: Fix size_t printf formart issue
>   librte_eal/common: Fix redeclaration of enumerator ‘REG_EAX’

v3 of each patch applied, thanks

Re: [dpdk-dev] [PATCH 1/3 v2] librte_hash: Fix unsupported instruction `crc32' in i686 platform

[Yerden Zhumabekov]

08.03.2015 0:39, Thomas Monjalon пишет:
> 2015-03-06 01:39, Qiu, Michael:
>> On 3/6/2015 1:11 AM, Thomas Monjalon wrote:
>>> 2015-03-06 00:55, Michael Qiu:
>>>> ... skipped ...
>>>>  
>>>> +#if defined RTE_ARCH_I686 || defined RTE_ARCH_X86_64
>>>>  static inline uint32_t
>>>>  crc32c_sse42_u32(uint32_t data, uint32_t init_val)
>>>>  {
>>>> @@ -373,7 +374,9 @@ crc32c_sse42_u32(uint32_t data, uint32_t init_val)
>>>>  			: [data] "rm" (data));
>>>>  	return init_val;
>>>>  }
>>>> +#endif
>>> Wouldn't it be more elegant to define a stub which returns 0 in #else
>>> in order to remove #ifdef below?
>>> Not sure, matter of taste.
>> It may be not a good idea, see rte_hash_crc_8byte(), if no crc32
>> support, it will use crc32c_2words(), if we define a stub which returns
>> 0 in #else, then we need always check the return value whether it is
>> none-zero otherwise need fallback.
> I don't think so.
> The stub won't never been called because they are protected by the cpuflag
> condition.

That would be a bad surprise if one tries to launch that pre-built
binary on SSE4.2-capable arch :) It's fine though, if binary portability
is out of scope here.

-- 
Sincerely,

Yerden Zhumabekov
State Technical Service
Astana, KZ

Re: [dpdk-dev] [PATCH 1/3 v3] librte_hash: Fix unsupported instruction `crc32' in i686 platform

[Liu, Yong]

Michael & Thomas,

Should we use software crc function replace of hardware crc function in 'crc32c_sse42_u64' when arch is i686?
Thus application still can use CRC32_SSE42_x64 algorithm for crc calculation when build with i686 configuration.
This may helpful for simplify application code.

> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Michael Qiu
> Sent: Monday, March 09, 2015 1:58 PM
> To: dev@dpdk.org
> Cc: yerden.zhumabekov@sts.kz
> Subject: [dpdk-dev] [PATCH 1/3 v3] librte_hash: Fix unsupported
> instruction `crc32' in i686 platform
> 
> CC rte_hash.o
> Error: unsupported instruction `crc32'
> 
> The root cause is that i686 platform does not support 'crc32q'
> Need make it only available in x86_64 platform
> 
> Signed-off-by: Michael Qiu <michael.qiu@intel.com>
> Acked-by: Yerden Zhumabekov <yerden.zhumabekov@sts.kz>
> ---
> v3 --> v2:
> 	Add sub function for #else which returns 0
> v2 --> v1:
>          Make crc32 instruction only works in X86 platform
> 
>  lib/librte_hash/rte_hash_crc.h | 46 +++++++++++++++++++++++++++++++++----
> -----
>  1 file changed, 36 insertions(+), 10 deletions(-)
> 
> diff --git a/lib/librte_hash/rte_hash_crc.h
> b/lib/librte_hash/rte_hash_crc.h
> index d28bb2a..f1dbded 100644
> --- a/lib/librte_hash/rte_hash_crc.h
> +++ b/lib/librte_hash/rte_hash_crc.h
> @@ -47,6 +47,7 @@ extern "C" {
>  #include <stdint.h>
>  #include <rte_cpuflags.h>
>  #include <rte_branch_prediction.h>
> +#include <rte_common.h>
> 
>  /* Lookup tables for software implementation of CRC32C */
>  static const uint32_t crc32c_tables[8][256] = {{
> @@ -364,6 +365,7 @@ crc32c_2words(uint64_t data, uint32_t init_val)
>  	return crc;
>  }
> 
> +#if defined(RTE_ARCH_I686) || defined(RTE_ARCH_X86_64)
>  static inline uint32_t
>  crc32c_sse42_u32(uint32_t data, uint32_t init_val)
>  {
> @@ -375,16 +377,6 @@ crc32c_sse42_u32(uint32_t data, uint32_t init_val)
>  }
> 
>  static inline uint32_t
> -crc32c_sse42_u64(uint64_t data, uint64_t init_val)
> -{
> -	__asm__ volatile(
> -			"crc32q %[data], %[init_val];"
> -			: [init_val] "+r" (init_val)
> -			: [data] "rm" (data));
> -	return init_val;
> -}
> -
> -static inline uint32_t
>  crc32c_sse42_u64_mimic(uint64_t data, uint64_t init_val)
>  {
>  	union {
> @@ -397,6 +389,40 @@ crc32c_sse42_u64_mimic(uint64_t data, uint64_t
> init_val)
>  	init_val = crc32c_sse42_u32(d.u32[1], init_val);
>  	return init_val;
>  }
> +#else
> +static inline uint32_t
> +crc32c_sse42_u32(__rte_unused uint32_t data,
> +		 __rte_unused uint32_t init_val)
> +{
> +	return 0;
> +}
> +
> +static inline uint32_t
> +crc32c_sse42_u64_mimic(__rte_unused uint32_t data,
> +		       __rte_unused uint32_t init_val)
> +{
> +	return 0;
> +}
> +#endif
> +
> +#ifdef RTE_ARCH_X86_64
> +static inline uint32_t
> +crc32c_sse42_u64(uint64_t data, uint64_t init_val)
> +{
> +	__asm__ volatile(
> +			"crc32q %[data], %[init_val];"
> +			: [init_val] "+r" (init_val)
> +			: [data] "rm" (data));
> +	return init_val;
> +}
> +#else
> +static inline uint32_t
> +crc32c_sse42_u64(__rte_unused uint64_t data,
> +		 __rte_unused uint64_t init_val)
> +{


	return crc32c_2words(data, init_val);


> +	return 0;
> +}
> +#endif
> 
>  #define CRC32_SW            (1U << 0)
>  #define CRC32_SSE42         (1U << 1)
> --
> 1.9.3

Re: [dpdk-dev] [PATCH 1/3 v3] librte_hash: Fix unsupported instruction `crc32' in i686 platform

[Qiu, Michael]

Hi, Yong

If the platform is i686, dpdk will use software crc function.

Thanks,
Michael

-----Original Message-----
From: Liu, Yong 
Sent: Wednesday, March 18, 2015 9:21 PM
To: Qiu, Michael; thomas.monjalon@6wind.com; dev@dpdk.org
Cc: yerden.zhumabekov@sts.kz
Subject: RE: [dpdk-dev] [PATCH 1/3 v3] librte_hash: Fix unsupported instruction `crc32' in i686 platform

Michael & Thomas,

Should we use software crc function replace of hardware crc function in 'crc32c_sse42_u64' when arch is i686?
Thus application still can use CRC32_SSE42_x64 algorithm for crc calculation when build with i686 configuration.
This may helpful for simplify application code.

> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Michael Qiu
> Sent: Monday, March 09, 2015 1:58 PM
> To: dev@dpdk.org
> Cc: yerden.zhumabekov@sts.kz
> Subject: [dpdk-dev] [PATCH 1/3 v3] librte_hash: Fix unsupported 
> instruction `crc32' in i686 platform
> 
> CC rte_hash.o
> Error: unsupported instruction `crc32'
> 
> The root cause is that i686 platform does not support 'crc32q'
> Need make it only available in x86_64 platform
> 
> Signed-off-by: Michael Qiu <michael.qiu@intel.com>
> Acked-by: Yerden Zhumabekov <yerden.zhumabekov@sts.kz>
> ---
> v3 --> v2:
> 	Add sub function for #else which returns 0
> v2 --> v1:
>          Make crc32 instruction only works in X86 platform
> 
>  lib/librte_hash/rte_hash_crc.h | 46 
> +++++++++++++++++++++++++++++++++----
> -----
>  1 file changed, 36 insertions(+), 10 deletions(-)
> 
> diff --git a/lib/librte_hash/rte_hash_crc.h 
> b/lib/librte_hash/rte_hash_crc.h index d28bb2a..f1dbded 100644
> --- a/lib/librte_hash/rte_hash_crc.h
> +++ b/lib/librte_hash/rte_hash_crc.h
> @@ -47,6 +47,7 @@ extern "C" {
>  #include <stdint.h>
>  #include <rte_cpuflags.h>
>  #include <rte_branch_prediction.h>
> +#include <rte_common.h>
> 
>  /* Lookup tables for software implementation of CRC32C */  static 
> const uint32_t crc32c_tables[8][256] = {{ @@ -364,6 +365,7 @@ 
> crc32c_2words(uint64_t data, uint32_t init_val)
>  	return crc;
>  }
> 
> +#if defined(RTE_ARCH_I686) || defined(RTE_ARCH_X86_64)
>  static inline uint32_t
>  crc32c_sse42_u32(uint32_t data, uint32_t init_val)  { @@ -375,16 
> +377,6 @@ crc32c_sse42_u32(uint32_t data, uint32_t init_val)  }
> 
>  static inline uint32_t
> -crc32c_sse42_u64(uint64_t data, uint64_t init_val) -{
> -	__asm__ volatile(
> -			"crc32q %[data], %[init_val];"
> -			: [init_val] "+r" (init_val)
> -			: [data] "rm" (data));
> -	return init_val;
> -}
> -
> -static inline uint32_t
>  crc32c_sse42_u64_mimic(uint64_t data, uint64_t init_val)  {
>  	union {
> @@ -397,6 +389,40 @@ crc32c_sse42_u64_mimic(uint64_t data, uint64_t
> init_val)
>  	init_val = crc32c_sse42_u32(d.u32[1], init_val);
>  	return init_val;
>  }
> +#else
> +static inline uint32_t
> +crc32c_sse42_u32(__rte_unused uint32_t data,
> +		 __rte_unused uint32_t init_val)
> +{
> +	return 0;
> +}
> +
> +static inline uint32_t
> +crc32c_sse42_u64_mimic(__rte_unused uint32_t data,
> +		       __rte_unused uint32_t init_val) {
> +	return 0;
> +}
> +#endif
> +
> +#ifdef RTE_ARCH_X86_64
> +static inline uint32_t
> +crc32c_sse42_u64(uint64_t data, uint64_t init_val) {
> +	__asm__ volatile(
> +			"crc32q %[data], %[init_val];"
> +			: [init_val] "+r" (init_val)
> +			: [data] "rm" (data));
> +	return init_val;
> +}
> +#else
> +static inline uint32_t
> +crc32c_sse42_u64(__rte_unused uint64_t data,
> +		 __rte_unused uint64_t init_val)
> +{


	return crc32c_2words(data, init_val);


> +	return 0;
> +}
> +#endif
> 
>  #define CRC32_SW            (1U << 0)
>  #define CRC32_SSE42         (1U << 1)
> --
> 1.9.3

Re: [dpdk-dev] [PATCH 1/3 v2] librte_hash: Fix unsupported instruction `crc32' in i686 platform

[Qiu, Michael]

On 3/8/2015 2:39 AM, Thomas Monjalon wrote:
> 2015-03-06 01:39, Qiu, Michael:
>> On 3/6/2015 1:11 AM, Thomas Monjalon wrote:
>>> 2015-03-06 00:55, Michael Qiu:
>>>> CC rte_hash.o
>>>> Error: unsupported instruction `crc32'
>>>>
>>>> The root cause is that i686 platform does not support 'crc32q'
>>>> Need make it only available in x86_64 platform
>>>>
>>>> Signed-off-by: Michael Qiu <michael.qiu@intel.com>
>>>> ---
>>>> v2 --> v1:
>>>>          Make crc32 instruction only works in X86 platform
>>>>  lib/librte_hash/rte_hash_crc.h | 12 ++++++++++++
>>>>  1 file changed, 12 insertions(+)
>>>>
>>>> diff --git a/lib/librte_hash/rte_hash_crc.h b/lib/librte_hash/rte_hash_crc.h
>>>> index d28bb2a..c0a789e 100644
>>>> --- a/lib/librte_hash/rte_hash_crc.h
>>>> +++ b/lib/librte_hash/rte_hash_crc.h
>>>> @@ -364,6 +364,7 @@ crc32c_2words(uint64_t data, uint32_t init_val)
>>>>  	return crc;
>>>>  }
>>>>  
>>>> +#if defined RTE_ARCH_I686 || defined RTE_ARCH_X86_64
>>>>  static inline uint32_t
>>>>  crc32c_sse42_u32(uint32_t data, uint32_t init_val)
>>>>  {
>>>> @@ -373,7 +374,9 @@ crc32c_sse42_u32(uint32_t data, uint32_t init_val)
>>>>  			: [data] "rm" (data));
>>>>  	return init_val;
>>>>  }
>>>> +#endif
>>> Wouldn't it be more elegant to define a stub which returns 0 in #else
>>> in order to remove #ifdef below?
>>> Not sure, matter of taste.
>> It may be not a good idea, see rte_hash_crc_8byte(), if no crc32
>> support, it will use crc32c_2words(), if we define a stub which returns
>> 0 in #else, then we need always check the return value whether it is
>> none-zero otherwise need fallback.
> I don't think so.
> The stub won't never been called because they are protected by the cpuflag
> condition.

Hi, Thomas

Indeed what I concerned occurs, when compile target i686 in X86_64
platform, it will call the stub function

Then, should I make a patch to fix, change the code as this one(V2)

Another choice is you could revert V3 and merge V2.

Or if have other solution?

Thanks,
Michael
>

Re: [dpdk-dev] [PATCH 1/3 v2] librte_hash: Fix unsupported instruction `crc32' in i686 platform

[Thomas Monjalon]

2015-03-19 02:00, Qiu, Michael:
> On 3/8/2015 2:39 AM, Thomas Monjalon wrote:
> > 2015-03-06 01:39, Qiu, Michael:
> >> On 3/6/2015 1:11 AM, Thomas Monjalon wrote:
> >>> 2015-03-06 00:55, Michael Qiu:
> >>>> CC rte_hash.o
> >>>> Error: unsupported instruction `crc32'
> >>>>
> >>>> The root cause is that i686 platform does not support 'crc32q'
> >>>> Need make it only available in x86_64 platform
> >>>>
> >>>> Signed-off-by: Michael Qiu <michael.qiu@intel.com>
> >>>> ---
> >>>> v2 --> v1:
> >>>>          Make crc32 instruction only works in X86 platform
> >>>>  lib/librte_hash/rte_hash_crc.h | 12 ++++++++++++
> >>>>  1 file changed, 12 insertions(+)
> >>>>
> >>>> diff --git a/lib/librte_hash/rte_hash_crc.h b/lib/librte_hash/rte_hash_crc.h
> >>>> index d28bb2a..c0a789e 100644
> >>>> --- a/lib/librte_hash/rte_hash_crc.h
> >>>> +++ b/lib/librte_hash/rte_hash_crc.h
> >>>> @@ -364,6 +364,7 @@ crc32c_2words(uint64_t data, uint32_t init_val)
> >>>>  	return crc;
> >>>>  }
> >>>>  
> >>>> +#if defined RTE_ARCH_I686 || defined RTE_ARCH_X86_64
> >>>>  static inline uint32_t
> >>>>  crc32c_sse42_u32(uint32_t data, uint32_t init_val)
> >>>>  {
> >>>> @@ -373,7 +374,9 @@ crc32c_sse42_u32(uint32_t data, uint32_t init_val)
> >>>>  			: [data] "rm" (data));
> >>>>  	return init_val;
> >>>>  }
> >>>> +#endif
> >>> Wouldn't it be more elegant to define a stub which returns 0 in #else
> >>> in order to remove #ifdef below?
> >>> Not sure, matter of taste.
> >> It may be not a good idea, see rte_hash_crc_8byte(), if no crc32
> >> support, it will use crc32c_2words(), if we define a stub which returns
> >> 0 in #else, then we need always check the return value whether it is
> >> none-zero otherwise need fallback.
> > I don't think so.
> > The stub won't never been called because they are protected by the cpuflag
> > condition.
> 
> Hi, Thomas
> 
> Indeed what I concerned occurs, when compile target i686 in X86_64
> platform, it will call the stub function

Oh, you mean compiling for i686 and run it in x86_64 target,
so the stub for crc32c_sse42_u64 is called?

> Then, should I make a patch to fix, change the code as this one(V2)
> Another choice is you could revert V3 and merge V2.
> Or if have other solution?

It's probably saner to submit a fix you have tested with ifdef like in v2.
Thanks