diff --git a/lib/librte_eal/linuxapp/igb_uio/igb_uio.c b/lib/librte_eal/linuxapp/igb_uio/igb_uio.c
index 05cbe8e..c5dbbe2 100644
--- a/lib/librte_eal/linuxapp/igb_uio/igb_uio.c
+++ b/lib/librte_eal/linuxapp/igb_uio/igb_uio.c
@@ -148,11 +148,11 @@ store_extended_tag(struct device *dev,
 	else
 		return -EINVAL;
 
-	pci_cfg_access_lock(pci_dev);
+	pci_block_user_cfg_access(pci_dev);
 	pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
 					PCI_DEV_CAP_REG, &val);
 	if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) { /* Not supported */
-		pci_cfg_access_unlock(pci_dev);
+		pci_unblock_user_cfg_access(pci_dev);
 		return -EPERM;
 	}
 
@@ -165,7 +165,7 @@ store_extended_tag(struct device *dev,
 		val &= ~PCI_DEV_CTRL_EXT_TAG_MASK;
 	pci_bus_write_config_dword(pci_dev->bus, pci_dev->devfn,
 					PCI_DEV_CTRL_REG, val);
-	pci_cfg_access_unlock(pci_dev);
+	pci_block_user_cfg_access(pci_dev);
 
 	return count;
 }
@@ -227,25 +227,26 @@ static const struct attribute_group dev_attr_grp = {
 /* Check if INTX works to control irq's.
  * Set's INTX_DISABLE flag and reads it back
  */
-static bool pci_intx_mask_supported(struct pci_dev *dev)
+static bool pci_intx_mask_supported(struct pci_dev *pdev)
 {
 	bool mask_supported = false;
-	uint16_t orig, new
+	uint16_t orig, new;
 
-	pci_block_user_cfg_access(dev);
+	pci_block_user_cfg_access(pdev);
 	pci_read_config_word(pdev, PCI_COMMAND, &orig);
-	pci_write_config_word(dev, PCI_COMMAND,
+	pci_write_config_word(pdev, PCI_COMMAND,
 			      orig ^ PCI_COMMAND_INTX_DISABLE);
-	pci_read_config_word(dev, PCI_COMMAND, &new);
+	pci_read_config_word(pdev, PCI_COMMAND, &new);
 
 	if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
-		dev_err(&dev->dev, "Command register changed from "
+		dev_err(&pdev->dev, "Command register changed from "
 			"0x%x to 0x%x: driver or hardware bug?\n", orig, new);
 	} else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
 		mask_supported = true;
-		pci_write_config_word(dev, PCI_COMMAND, orig);
+		pci_write_config_word(pdev, PCI_COMMAND, orig);
 	}
-	pci_unblock_user_cfg_access(dev);
+	pci_unblock_user_cfg_access(pdev);
+	return mask_supported;
 }
 
 static bool pci_check_and_mask_intx(struct pci_dev *pdev)
@@ -253,7 +254,7 @@ static bool pci_check_and_mask_intx(struct pci_dev *pdev)
 	bool pending;
 	uint32_t status;
 
-	pci_block_user_cfg_access(dev);
+	pci_block_user_cfg_access(pdev);
 	pci_read_config_dword(pdev, PCI_COMMAND, &status);
 
 	/* interrupt is not ours, goes to out */
@@ -262,7 +263,7 @@ static bool pci_check_and_mask_intx(struct pci_dev *pdev)
 		uint16_t old, new;
 
 		old = status;
-		if (state != 0)
+		if (status != 0)
 			new = old & (~PCI_COMMAND_INTX_DISABLE);
 		else
 			new = old | PCI_COMMAND_INTX_DISABLE;
@@ -270,7 +271,7 @@ static bool pci_check_and_mask_intx(struct pci_dev *pdev)
 		if (old != new)
 			pci_write_config_word(pdev, PCI_COMMAND, new);
 	}
-	pci_unblock_user_cfg_access(dev);
+	pci_unblock_user_cfg_access(pdev);
 
 	return pending;
 }
@@ -335,7 +336,7 @@ igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
 	struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
 	struct pci_dev *pdev = udev->pdev;
 
-	pci_cfg_access_lock(pdev);
+	pci_block_user_cfg_access(pdev);
 	if (udev->mode == RTE_INTR_MODE_LEGACY)
 		pci_intx(pdev, !!irq_state);
 	else if (udev->mode == RTE_INTR_MODE_MSI) {
@@ -348,7 +349,7 @@ igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
 		list_for_each_entry(desc, &pdev->msi_list, list)
 			igbuio_msix_mask_irq(desc, irq_state);
 	}
-	pci_cfg_access_unlock(pdev);
+	pci_unblock_user_cfg_access(pdev);
 
 	return 0;
 }