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From: Gyumin <hkm73560@gmail.com>
To: dev@dpdk.org
Subject: [dpdk-dev] Relationship between H/W ring and S/W ring
Date: Thu, 30 Oct 2014 16:32:16 +0900
Message-ID: <5451E980.2060707@gmail.com> (raw)


I`m reading the ixgbe code especially about H/W ring and S/W ring. Is 
the relationship between H/W ring and S/W ring one-to-one mapping?
As far as I know, H/W ring size is determined in the code(hard coded) 
while S/W ring size is determined in port configuration time.
In the ixgbe_rx_alloc_bufs function, H/W ring header address and packet 
address indicate the DMA address of S/W ring's mbuf. I understand it 
means that the relationship between the H/W ring and S/W ring is 
one-to-one mapping. For example, if the size of H/W ring is greater than 
the size of  S/W ring then some portion of H/W ring is unused. Is it 


             reply	other threads:[~2014-10-30  7:25 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-10-30  7:32 Gyumin [this message]
2014-10-30  9:55 ` Bruce Richardson
2014-10-31  0:51   ` Gyumin
2014-10-31 10:08     ` Bruce Richardson
2014-11-01 13:52       ` GyuminHwang

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