From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgw.gov.kz (mgw.gov.kz [89.218.88.242]) by dpdk.org (Postfix) with ESMTP id 8484B595B for ; Wed, 19 Nov 2014 04:57:50 +0100 (CET) Received: from mgw.gov.kz (mx.ctsat.kz [178.89.4.95]) by mgw.gov.kz with ESMTP id sAJ486EI016124-sAJ486EK016124 (version=TLSv1.0 cipher=AES128-SHA bits=128 verify=NO); Wed, 19 Nov 2014 10:08:06 +0600 Received: from EXCASHUB1.rgp.local (192.168.40.51) by EdgeForefront.rgp.local (192.168.40.59) with Microsoft SMTP Server (TLS) id 14.2.247.3; Wed, 19 Nov 2014 10:07:54 +0600 Received: from [192.168.35.15] (192.168.35.15) by excashub1.rgp.local (192.168.40.48) with Microsoft SMTP Server (TLS) id 14.2.247.3; Wed, 19 Nov 2014 10:08:07 +0600 Message-ID: <546C177B.10003@sts.kz> Date: Wed, 19 Nov 2014 10:07:23 +0600 From: Yerden Zhumabekov User-Agent: Mozilla/5.0 (Windows NT 6.3; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: "Wang, Shawn" , "dev@dpdk.org" References: <1409724351-23786-1-git-send-email-e_zhumabekov@sts.kz> <20141118144138.GB32375@hmsreliant.think-freely.org> <546B607B.9030808@sts.kz> <20141118160005.GC32375@hmsreliant.think-freely.org>, <546B7E2D.7050705@sts.kz> <12C2AAD9525203489F7B523D670129D91CCF3615@ex10-mbx-31007.ant.amazon.com> In-Reply-To: <12C2AAD9525203489F7B523D670129D91CCF3615@ex10-mbx-31007.ant.amazon.com> Content-Type: text/plain; charset="koi8-r" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [192.168.35.15] X-FEAS-SYSTEM-WL: e_zhumabekov@sts.kz Subject: Re: [dpdk-dev] [PATCH v4 3/5] hash: add fallback to software CRC32 implementation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 19 Nov 2014 03:57:51 -0000 18.11.2014 23:29, Wang, Shawn =D0=C9=DB=C5=D4: > I have a general question about using CPUID to detect supported instruc= tion set. > What if we are compiling the software with some old hardware which does= not support SSE4.2, but run it on new hardware which does support SSE4.2= =2E Is there still a static way to force the compiler to turn on the SSE4= =2E2 support?=20 > I guess for SSE4.2, most of the CPU has support for it now. But for AVX= 2, this might not be the case. According to gcc 4.7 changes (https://gcc.gnu.org/gcc-4.7/changes.html) they've added support for AVX2 instructions since that version. Use -mavx2 or -march=3Dcore-avx2. The latter seems to be supported by ICC= as well, according to Google :) --=20 Sincerely, Yerden Zhumabekov State Technical Service Astana, KZ