From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from e23smtp09.au.ibm.com (e23smtp09.au.ibm.com [202.81.31.142]) by dpdk.org (Postfix) with ESMTP id 968627E0C for ; Wed, 26 Nov 2014 03:24:05 +0100 (CET) Received: from /spool/local by e23smtp09.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Wed, 26 Nov 2014 12:34:56 +1000 Received: from d23dlp01.au.ibm.com (202.81.31.203) by e23smtp09.au.ibm.com (202.81.31.206) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Wed, 26 Nov 2014 12:34:55 +1000 Received: from d23relay08.au.ibm.com (d23relay08.au.ibm.com [9.185.71.33]) by d23dlp01.au.ibm.com (Postfix) with ESMTP id BEA632CE805B for ; Wed, 26 Nov 2014 13:34:54 +1100 (EST) Received: from d23av04.au.ibm.com (d23av04.au.ibm.com [9.190.235.139]) by d23relay08.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id sAQ2YnZk40894498 for ; Wed, 26 Nov 2014 13:34:50 +1100 Received: from d23av04.au.ibm.com (localhost [127.0.0.1]) by d23av04.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id sAQ2YsbW010617 for ; Wed, 26 Nov 2014 13:34:54 +1100 Received: from [127.0.0.1] ([9.186.59.193]) by d23av04.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id sAQ2YotO010492; Wed, 26 Nov 2014 13:34:53 +1100 Message-ID: <54753C75.3080503@linux.vnet.ibm.com> Date: Wed, 26 Nov 2014 10:35:33 +0800 From: Chao Zhu User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: "Qiu, Michael" , "dev@dpdk.org" References: <1416792142-23132-1-git-send-email-chaozhu@linux.vnet.ibm.com> <1416792142-23132-4-git-send-email-chaozhu@linux.vnet.ibm.com> <533710CFB86FA344BFBF2D6802E60286C99F43@SHSMSX101.ccr.corp.intel.com> In-Reply-To: <533710CFB86FA344BFBF2D6802E60286C99F43@SHSMSX101.ccr.corp.intel.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 14112602-0033-0000-0000-0000009889C5 Subject: Re: [dpdk-dev] [PATCH v3 03/14] Add byte order operations for IBM Power architecture X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 26 Nov 2014 02:24:07 -0000 Michael, The default endianess of Power7/8 is big endian. So I set big endian in the configuration file. If use little endian, just change the configuration file. Of cause, there is some way to determine the endian in run time. However, the original DPDK didn't do this. I think this can be improved later. About your second question, Power7 can support little endian, but it is a emulated one, not a CPU hardware feature. Also, there is no official little endian support for Power7. So I marked Power7 only support big endian. On 2014/11/24 16:11, Qiu, Michael wrote: > On 11/23/2014 9:22 PM, Chao Zhu wrote: >> This patch adds architecture specific byte order operations for IBM Power >> architecture. Power architecture support both big endian and little >> endian. This patch also adds a RTE_ARCH_BIG_ENDIAN micro. >> >> Signed-off-by: Chao Zhu >> --- >> config/defconfig_ppc_64-power8-linuxapp-gcc | 1 + >> .../common/include/arch/ppc_64/rte_byteorder.h | 150 ++++++++++++++++++++ >> 2 files changed, 151 insertions(+), 0 deletions(-) >> create mode 100644 lib/librte_eal/common/include/arch/ppc_64/rte_byteorder.h >> >> diff --git a/config/defconfig_ppc_64-power8-linuxapp-gcc b/config/defconfig_ppc_64-power8-linuxapp-gcc >> index 97d72ff..b10f60c 100644 >> --- a/config/defconfig_ppc_64-power8-linuxapp-gcc >> +++ b/config/defconfig_ppc_64-power8-linuxapp-gcc >> @@ -34,6 +34,7 @@ CONFIG_RTE_MACHINE="power8" >> >> CONFIG_RTE_ARCH="ppc_64" >> CONFIG_RTE_ARCH_PPC_64=y >> +CONFIG_RTE_ARCH_BIG_ENDIAN=y > Does this means default is Big Endian, if I runs it in little endian > mode, I need to change it manually? >> >> CONFIG_RTE_TOOLCHAIN="gcc" >> CONFIG_RTE_TOOLCHAIN_GCC=y >> diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_byteorder.h b/lib/librte_eal/common/include/arch/ppc_64/rte_byteorder.h >> new file mode 100644 >> index 0000000..a593e8a >> --- /dev/null >> +++ b/lib/librte_eal/common/include/arch/ppc_64/rte_byteorder.h >> @@ -0,0 +1,150 @@ >> +/* >> + * BSD LICENSE >> + * >> + * Copyright (C) IBM Corporation 2014. >> + * >> + * Redistribution and use in source and binary forms, with or without >> + * modification, are permitted provided that the following conditions >> + * are met: >> + * >> + * * Redistributions of source code must retain the above copyright >> + * notice, this list of conditions and the following disclaimer. >> + * * Redistributions in binary form must reproduce the above copyright >> + * notice, this list of conditions and the following disclaimer in >> + * the documentation and/or other materials provided with the >> + * distribution. >> + * * Neither the name of IBM Corporation nor the names of its >> + * contributors may be used to endorse or promote products derived >> + * from this software without specific prior written permission. >> + * >> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS >> + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT >> + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR >> + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT >> + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, >> + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT >> + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, >> + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY >> + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT >> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE >> + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. >> +*/ >> + >> +/* Inspired from FreeBSD src/sys/powerpc/include/endian.h >> + * Copyright (c) 1987, 1991, 1993 >> + * The Regents of the University of California. All rights reserved. >> +*/ >> + >> +#ifndef _RTE_BYTEORDER_PPC_64_H_ >> +#define _RTE_BYTEORDER_PPC_64_H_ >> + >> +#ifdef __cplusplus >> +extern "C" { >> +#endif >> + >> +#include "generic/rte_byteorder.h" >> + >> +/* >> + * An architecture-optimized byte swap for a 16-bit value. >> + * >> + * Do not use this function directly. The preferred function is rte_bswap16(). >> + */ >> +static inline uint16_t rte_arch_bswap16(uint16_t _x) >> +{ >> + return ((_x >> 8) | ((_x << 8) & 0xff00)); >> +} >> + >> +/* >> + * An architecture-optimized byte swap for a 32-bit value. >> + * >> + * Do not use this function directly. The preferred function is rte_bswap32(). >> + */ >> +static inline uint32_t rte_arch_bswap32(uint32_t _x) >> +{ >> + return ((_x >> 24) | ((_x >> 8) & 0xff00) | ((_x << 8) & 0xff0000) | >> + ((_x << 24) & 0xff000000)); >> +} >> + >> +/* >> + * An architecture-optimized byte swap for a 64-bit value. >> + * >> + * Do not use this function directly. The preferred function is rte_bswap64(). >> + */ >> +/* 64-bit mode */ >> +static inline uint64_t rte_arch_bswap64(uint64_t _x) >> +{ >> + return ((_x >> 56) | ((_x >> 40) & 0xff00) | ((_x >> 24) & 0xff0000) | >> + ((_x >> 8) & 0xff000000) | ((_x << 8) & (0xffULL << 32)) | >> + ((_x << 24) & (0xffULL << 40)) | >> + ((_x << 40) & (0xffULL << 48)) | ((_x << 56))); >> +} >> + >> +#ifndef RTE_FORCE_INTRINSICS >> +#define rte_bswap16(x) ((uint16_t)(__builtin_constant_p(x) ? \ >> + rte_constant_bswap16(x) : \ >> + rte_arch_bswap16(x))) >> + >> +#define rte_bswap32(x) ((uint32_t)(__builtin_constant_p(x) ? \ >> + rte_constant_bswap32(x) : \ >> + rte_arch_bswap32(x))) >> + >> +#define rte_bswap64(x) ((uint64_t)(__builtin_constant_p(x) ? \ >> + rte_constant_bswap64(x) : \ >> + rte_arch_bswap64(x))) >> +#else >> +/* >> + * __builtin_bswap16 is only available gcc 4.8 and upwards >> + */ >> +#if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 8) >> +#define rte_bswap16(x) ((uint16_t)(__builtin_constant_p(x) ? \ >> + rte_constant_bswap16(x) : \ >> + rte_arch_bswap16(x))) >> +#endif >> +#endif >> + >> +/* Power 8 have both little endian and big endian mode >> + * Power 7 only support big endian > Are you sure about this ? What I've heard is that all power CPU(at least > Power7 and 8) supports, but not check the spec. >> + */ >> +#ifndef RTE_ARCH_BIG_ENDIAN >> + >> +#define rte_cpu_to_le_16(x) (x) >> +#define rte_cpu_to_le_32(x) (x) >> +#define rte_cpu_to_le_64(x) (x) >> + >> +#define rte_cpu_to_be_16(x) rte_bswap16(x) >> +#define rte_cpu_to_be_32(x) rte_bswap32(x) >> +#define rte_cpu_to_be_64(x) rte_bswap64(x) >> + >> +#define rte_le_to_cpu_16(x) (x) >> +#define rte_le_to_cpu_32(x) (x) >> +#define rte_le_to_cpu_64(x) (x) >> + >> +#define rte_be_to_cpu_16(x) rte_bswap16(x) >> +#define rte_be_to_cpu_32(x) rte_bswap32(x) >> +#define rte_be_to_cpu_64(x) rte_bswap64(x) >> + >> +#else >> + >> +#define rte_cpu_to_le_16(x) rte_bswap16(x) >> +#define rte_cpu_to_le_32(x) rte_bswap32(x) >> +#define rte_cpu_to_le_64(x) rte_bswap64(x) >> + >> +#define rte_cpu_to_be_16(x) (x) >> +#define rte_cpu_to_be_32(x) (x) >> +#define rte_cpu_to_be_64(x) (x) >> + >> +#define rte_le_to_cpu_16(x) rte_bswap16(x) >> +#define rte_le_to_cpu_32(x) rte_bswap32(x) >> +#define rte_le_to_cpu_64(x) rte_bswap64(x) >> + >> +#define rte_be_to_cpu_16(x) (x) >> +#define rte_be_to_cpu_32(x) (x) >> +#define rte_be_to_cpu_64(x) (x) >> +#endif >> + >> +#ifdef __cplusplus >> +} >> +#endif >> + >> +#endif /* _RTE_BYTEORDER_PPC_64_H_ */ >> + >