From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5B4B3A04AC; Fri, 1 May 2020 13:33:49 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id ED1FC1DA3A; Fri, 1 May 2020 13:33:48 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id BEB311DA2C for ; Fri, 1 May 2020 13:33:47 +0200 (CEST) IronPort-SDR: 8gJYB4Roco7jiPMbvQKpz/stGBLnpPTr4oo0nF8svcmOtozoVpQaqQ2JvfV4HLIgu/lUqzEOpJ PI/Fprr/Krnw== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 May 2020 04:33:46 -0700 IronPort-SDR: 49K3L6ejIM+Mwwex0tvxOuc6pV9rzR4lRf4hKFRbHUeFTjv7n/dbcZDGcJrht5LtsbUk01nyy5 GAS2iCPwsGRA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,339,1583222400"; d="scan'208";a="459886712" Received: from fyigit-mobl.ger.corp.intel.com (HELO [10.252.12.222]) ([10.252.12.222]) by fmsmga005.fm.intel.com with ESMTP; 01 May 2020 04:33:45 -0700 To: ssardar@amd.com, dev@dpdk.org References: <20200430065930.124067-1-ssardar@amd.com> From: Ferruh Yigit Autocrypt: addr=ferruh.yigit@intel.com; prefer-encrypt=mutual; keydata= mQINBFXZCFABEADCujshBOAaqPZpwShdkzkyGpJ15lmxiSr3jVMqOtQS/sB3FYLT0/d3+bvy qbL9YnlbPyRvZfnP3pXiKwkRoR1RJwEo2BOf6hxdzTmLRtGtwWzI9MwrUPj6n/ldiD58VAGQ +iR1I/z9UBUN/ZMksElA2D7Jgg7vZ78iKwNnd+vLBD6I61kVrZ45Vjo3r+pPOByUBXOUlxp9 GWEKKIrJ4eogqkVNSixN16VYK7xR+5OUkBYUO+sE6etSxCr7BahMPKxH+XPlZZjKrxciaWQb +dElz3Ab4Opl+ZT/bK2huX+W+NJBEBVzjTkhjSTjcyRdxvS1gwWRuXqAml/sh+KQjPV1PPHF YK5LcqLkle+OKTCa82OvUb7cr+ALxATIZXQkgmn+zFT8UzSS3aiBBohg3BtbTIWy51jNlYdy ezUZ4UxKSsFuUTPt+JjHQBvF7WKbmNGS3fCid5Iag4tWOfZoqiCNzxApkVugltxoc6rG2TyX CmI2rP0mQ0GOsGXA3+3c1MCdQFzdIn/5tLBZyKy4F54UFo35eOX8/g7OaE+xrgY/4bZjpxC1 1pd66AAtKb3aNXpHvIfkVV6NYloo52H+FUE5ZDPNCGD0/btFGPWmWRmkPybzColTy7fmPaGz cBcEEqHK4T0aY4UJmE7Ylvg255Kz7s6wGZe6IR3N0cKNv++O7QARAQABtCVGZXJydWggWWln aXQgPGZlcnJ1aC55aWdpdEBpbnRlbC5jb20+iQJsBBMBCgBWAhsDAh4BAheABQsJCAcDBRUK CQgLBRYCAwEABQkKqZZ8FiEE0jZTh0IuwoTjmYHH+TPrQ98TYR8FAl6ha3sXGHZrczovL2tl eXMub3BlbnBncC5vcmcACgkQ+TPrQ98TYR8uLA//QwltuFliUWe60xwmu9sY38c1DXvX67wk UryQ1WijVdIoj4H8cf/s2KtyIBjc89R254KMEfJDao/LrXqJ69KyGKXFhFPlF3VmFLsN4XiT PSfxkx8s6kHVaB3O183p4xAqnnl/ql8nJ5ph9HuwdL8CyO5/7dC/MjZ/mc4NGq5O9zk3YRGO lvdZAp5HW9VKW4iynvy7rl3tKyEqaAE62MbGyfJDH3C/nV/4+mPc8Av5rRH2hV+DBQourwuC ci6noiDP6GCNQqTh1FHYvXaN4GPMHD9DX6LtT8Fc5mL/V9i9kEVikPohlI0WJqhE+vQHFzR2 1q5nznE+pweYsBi3LXIMYpmha9oJh03dJOdKAEhkfBr6n8BWkWQMMiwfdzg20JX0o7a/iF8H 4dshBs+dXdIKzPfJhMjHxLDFNPNH8zRQkB02JceY9ESEah3wAbzTwz+e/9qQ5OyDTQjKkVOo cxC2U7CqeNt0JZi0tmuzIWrfxjAUulVhBmnceqyMOzGpSCQIkvalb6+eXsC9V1DZ4zsHZ2Mx Hi+7pCksdraXUhKdg5bOVCt8XFmx1MX4AoV3GWy6mZ4eMMvJN2hjXcrreQgG25BdCdcxKgqp e9cMbCtF+RZax8U6LkAWueJJ1QXrav1Jk5SnG8/5xANQoBQKGz+yFiWcgEs9Tpxth15o2v59 gXK5Ag0EV9ZMvgEQAKc0Db17xNqtSwEvmfp4tkddwW9XA0tWWKtY4KUdd/jijYqc3fDD54ES YpV8QWj0xK4YM0dLxnDU2IYxjEshSB1TqAatVWz9WtBYvzalsyTqMKP3w34FciuL7orXP4Ai bPtrHuIXWQOBECcVZTTOdZYGAzaYzxiAONzF9eTiwIqe9/oaOjTwTLnOarHt16QApTYQSnxD UQljeNvKYt1lZE/gAUUxNLWsYyTT+22/vU0GDUahsJxs1+f1yEr+OGrFiEAmqrzpF0lCS3f/ 3HVTU6rS9cK3glVUeaTF4+1SK5ZNO35piVQCwphmxa+dwTG/DvvHYCtgOZorTJ+OHfvCnSVj sM4kcXGjJPy3JZmUtyL9UxEbYlrffGPQI3gLXIGD5AN5XdAXFCjjaID/KR1c9RHd7Oaw0Pdc q9UtMLgM1vdX8RlDuMGPrj5sQrRVbgYHfVU/TQCk1C9KhzOwg4Ap2T3tE1umY/DqrXQgsgH7 1PXFucVjOyHMYXXugLT8YQ0gcBPHy9mZqw5mgOI5lCl6d4uCcUT0l/OEtPG/rA1lxz8ctdFB VOQOxCvwRG2QCgcJ/UTn5vlivul+cThi6ERPvjqjblLncQtRg8izj2qgmwQkvfj+h7Ex88bI 8iWtu5+I3K3LmNz/UxHBSWEmUnkg4fJlRr7oItHsZ0ia6wWQ8lQnABEBAAGJAjwEGAEKACYC GwwWIQTSNlOHQi7ChOOZgcf5M+tD3xNhHwUCXqFrngUJCKxSYAAKCRD5M+tD3xNhH3YWD/9b cUiWaHJasX+OpiuZ1Li5GG3m9aw4lR/k2lET0UPRer2Jy1JsL+uqzdkxGvPqzFTBXgx/6Byz EMa2mt6R9BCyR286s3lxVS5Bgr5JGB3EkpPcoJT3A7QOYMV95jBiiJTy78Qdzi5LrIu4tW6H o0MWUjpjdbR01cnj6EagKrDx9kAsqQTfvz4ff5JIFyKSKEHQMaz1YGHyCWhsTwqONhs0G7V2 0taQS1bGiaWND0dIBJ/u0pU998XZhmMzn765H+/MqXsyDXwoHv1rcaX/kcZIcN3sLUVcbdxA WHXOktGTQemQfEpCNuf2jeeJlp8sHmAQmV3dLS1R49h0q7hH4qOPEIvXjQebJGs5W7s2vxbA 5u5nLujmMkkfg1XHsds0u7Zdp2n200VC4GQf8vsUp6CSMgjedHeF9zKv1W4lYXpHp576ZV7T GgsEsvveAE1xvHnpV9d7ZehPuZfYlP4qgo2iutA1c0AXZLn5LPcDBgZ+KQZTzm05RU1gkx7n gL9CdTzVrYFy7Y5R+TrE9HFUnsaXaGsJwOB/emByGPQEKrupz8CZFi9pkqPuAPwjN6Wonokv ChAewHXPUadcJmCTj78Oeg9uXR6yjpxyFjx3vdijQIYgi5TEGpeTQBymLANOYxYWYOjXk+ae dYuOYKR9nbPv+2zK9pwwQ2NXbUBystaGyQ== Message-ID: <5528f7ad-2731-6a23-20ee-78bcbf3328b6@intel.com> Date: Fri, 1 May 2020 12:33:44 +0100 MIME-Version: 1.0 In-Reply-To: <20200430065930.124067-1-ssardar@amd.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Subject: Re: [dpdk-dev] [PATCH v3] net/axgbe: enabling VLAN support in axgbe X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 4/30/2020 7:59 AM, ssardar@amd.com wrote: > From: Sardar Shamsher Singh > > adding below APIs for axgbe > - axgbe_enable_rx_vlan_stripping: to enable vlan header stipping > - axgbe_disable_rx_vlan_stripping: to disable vlan header stipping > - axgbe_enable_rx_vlan_filtering: to enable vlan filter mode > - axgbe_disable_rx_vlan_filtering: to disable vlan filter mode > - axgbe_update_vlan_hash_table: crc calculation and hash table update > based on vlan values post filter enable > - axgbe_vlan_filter_set: setting of active vlan out of max 4K values before > doing hash update of same > - axgbe_vlan_tpid_set: setting of default tpid values > - axgbe_vlan_offload_set: a top layer function to call stip/filter etc > based on mask values > > Signed-off-by: Sardar Shamsher Singh <...> > +static int > +axgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask) > +{ > + struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; > + struct axgbe_port *pdata = dev->data->dev_private; > + > + /* Indicate that VLAN Tx CTAGs come from context descriptors */ > + AXGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0); > + AXGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1); > + > + if (mask & ETH_VLAN_STRIP_MASK) { > + if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { > + PMD_DRV_LOG(DEBUG, "Strip ON for device = %s\n", > + pdata->eth_dev->device->name); > + pdata->hw_if.enable_rx_vlan_stripping(pdata); > + } else { > + PMD_DRV_LOG(DEBUG, "Strip OFF for device = %s\n", > + pdata->eth_dev->device->name); > + pdata->hw_if.disable_rx_vlan_stripping(pdata); > + } > + } > + if (mask & ETH_VLAN_FILTER_MASK) { > + if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { > + PMD_DRV_LOG(DEBUG, "Filter ON for device = %s\n", > + pdata->eth_dev->device->name); > + pdata->hw_if.enable_rx_vlan_filtering(pdata); > + } else { > + PMD_DRV_LOG(DEBUG, "Filter OFF for device = %s\n", > + pdata->eth_dev->device->name); > + pdata->hw_if.disable_rx_vlan_filtering(pdata); > + } > + } > + if (mask & ETH_VLAN_EXTEND_MASK) { > + if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) { > + PMD_DRV_LOG(DEBUG, "enabling vlan extended mode\n"); > + axgbe_vlan_extend_enable(pdata); > + /* Set global registers with default ethertype*/ > + axgbe_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, > + RTE_ETHER_TYPE_VLAN); > + axgbe_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER, > + RTE_ETHER_TYPE_VLAN); > + } else { > + PMD_DRV_LOG(DEBUG, "disabling vlan extended mode\n"); > + axgbe_vlan_extend_disable(pdata); > + } > + } Is the intention here to enable disable QinQ stip, because enable/disable fucntions talks about qinq, if so 'ETH_QINQ_STRIP_MASK' should be used. <...> > @@ -275,6 +275,23 @@ axgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, > /* Get the RSS hash */ > if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, RSV)) > mbuf->hash.rss = rte_le_to_cpu_32(desc->write.desc1); > + etlt = AXGMAC_GET_BITS_LE(desc->write.desc3, > + RX_NORMAL_DESC3, ETLT); > + if (!err || !etlt) { > + if (etlt == 0x09 && > + (rxq->pdata->eth_dev->data->dev_conf.rxmode.offloads & > + DEV_RX_OFFLOAD_VLAN_STRIP)) { > + mbuf->ol_flags |= > + PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED; > + mbuf->vlan_tci = > + AXGMAC_GET_BITS_LE(desc->write.desc0, > + RX_NORMAL_DESC0, OVT); I don't know HW capabilities, but if 'etlt == 0x09' means packet has VLAN tag, you can use it independent from strip, like below, up to you. if (vlan) { mbuf->ol_flags |= PKT_RX_VLAN; mbuf->vlan_tci = xxx if (vlan_stripped) { mbuf->ol_flags |= PKT_RX_VLAN_STRIPPED; } } <...> > @@ -487,6 +520,7 @@ int axgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, > struct axgbe_tx_queue *txq; > unsigned int tsize; > const struct rte_memzone *tz; > + uint64_t offloads; > > tx_desc = nb_desc; > pdata = dev->data->dev_private; > @@ -506,7 +540,8 @@ int axgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, > if (!txq) > return -ENOMEM; > txq->pdata = pdata; > - > + offloads = tx_conf->offloads | > + txq->pdata->eth_dev->data->dev_conf.txmode.offloads; As far as I can see PMD doesn't support queue specific offloads, so 'tx_conf->offloads' should be always 0. And since there is no queue specific offload and this 'offloads' information is only used to set burst function, which is again only port bases (this will keep overwrite same info per each queue), why not do this check in the 'axgbe_dev_configure()' instead of per queue? And I can see you may hit the problem becuase of VLAN offload but the issue seems generic, not directly related to VLAN support, and this can be separate fix I think.