From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C177AA034F; Sun, 6 Jun 2021 16:18:02 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4212F40040; Sun, 6 Jun 2021 16:18:02 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 2205D4003F for ; Sun, 6 Jun 2021 16:17:59 +0200 (CEST) IronPort-SDR: 0A9Z4ZYVVcW4A4VVHvarEcn6VL96C4ocwFRMOwaHxsE6AiPBZ0zg5w1RRhOgzn6iJo7cLMQekD Zlq/ewEPwyxQ== X-IronPort-AV: E=McAfee;i="6200,9189,10007"; a="265667420" X-IronPort-AV: E=Sophos;i="5.83,253,1616482800"; d="scan'208";a="265667420" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2021 07:17:58 -0700 IronPort-SDR: jUCjQcQSgdRt0MuHMkGrq+wcn7yTt6KKM9TkcFy0rHQN1819AC4ZJuFMDFtk2O2Fxm7ZRbPQiT bfqiVYHtnOdQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.83,253,1616482800"; d="scan'208";a="439753017" Received: from fmsmsx601.amr.corp.intel.com ([10.18.126.81]) by orsmga007.jf.intel.com with ESMTP; 06 Jun 2021 07:17:58 -0700 Received: from shsmsx603.ccr.corp.intel.com (10.109.6.143) by fmsmsx601.amr.corp.intel.com (10.18.126.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.4; Sun, 6 Jun 2021 07:17:57 -0700 Received: from shsmsx601.ccr.corp.intel.com (10.109.6.141) by SHSMSX603.ccr.corp.intel.com (10.109.6.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.4; Sun, 6 Jun 2021 22:17:56 +0800 Received: from shsmsx601.ccr.corp.intel.com ([10.109.6.141]) by SHSMSX601.ccr.corp.intel.com ([10.109.6.141]) with mapi id 15.01.2242.008; Sun, 6 Jun 2021 22:17:55 +0800 From: "Zhang, Qi Z" To: Joyce Kong , "Xing, Beilei" , "ruifeng.wang@arm.com" , "honnappa.nagarahalli@arm.com" CC: "dev@dpdk.org" , "nd@arm.com" Thread-Topic: [PATCH v1] net/i40e: remove the SMP barrier in HW scanning func Thread-Index: AQHXWRQSr5j0Y9t8tEik4BdoB++ri6sHBN4w Date: Sun, 6 Jun 2021 14:17:55 +0000 Message-ID: <561469a10f13450bae9e857f186b0123@intel.com> References: <20210604073405.14880-1-joyce.kong@arm.com> In-Reply-To: <20210604073405.14880-1-joyce.kong@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.5.1.3 dlp-product: dlpe-windows x-originating-ip: [10.239.127.36] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v1] net/i40e: remove the SMP barrier in HW scanning func X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Joyce Kong > Sent: Friday, June 4, 2021 3:34 PM > To: Xing, Beilei ; Zhang, Qi Z ; > ruifeng.wang@arm.com; honnappa.nagarahalli@arm.com > Cc: dev@dpdk.org; nd@arm.com > Subject: [PATCH v1] net/i40e: remove the SMP barrier in HW scanning func >=20 > Add the logic to determine how many DD bits have been set for contiguous > packets, for removing the SMP barrier while reading descs. I didn't understand this. The current logic already guarantee the read out DD bits are from continue = packets, as it read Rx descriptor in a reversed order from the ring. So I didn't see the a new logic be added, would you describe more clear abo= ut the purpose of this patch? >=20 > Signed-off-by: Joyce Kong > Reviewed-by: Ruifeng Wang > --- > drivers/net/i40e/i40e_rxtx.c | 13 ++++++++----- > 1 file changed, 8 insertions(+), 5 deletions(-) >=20 > diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c = index > 6c58decec..410a81f30 100644 > --- a/drivers/net/i40e/i40e_rxtx.c > +++ b/drivers/net/i40e/i40e_rxtx.c > @@ -452,7 +452,7 @@ i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq) > uint16_t pkt_len; > uint64_t qword1; > uint32_t rx_status; > - int32_t s[I40E_LOOK_AHEAD], nb_dd; > + int32_t s[I40E_LOOK_AHEAD], var, nb_dd; > int32_t i, j, nb_rx =3D 0; > uint64_t pkt_flags; > uint32_t *ptype_tbl =3D rxq->vsi->adapter->ptype_tbl; @@ -482,11 +482,1= 4 > @@ i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq) > I40E_RXD_QW1_STATUS_SHIFT; > } >=20 > - rte_smp_rmb(); Any performance gain by removing this? and it is not necessary to be combin= ed with below change, right? =20 > - > /* Compute how many status bits were set */ > - for (j =3D 0, nb_dd =3D 0; j < I40E_LOOK_AHEAD; j++) > - nb_dd +=3D s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT); > + for (j =3D 0, nb_dd =3D 0; j < I40E_LOOK_AHEAD; j++) { > + var =3D s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT); > + if (var) > + nb_dd +=3D 1; > + else > + break; > + } >=20 > nb_rx +=3D nb_dd; >=20 > -- > 2.17.1