From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by dpdk.org (Postfix) with ESMTP id 3AA438EA1 for ; Fri, 22 Jan 2016 11:06:02 +0100 (CET) Received: from int-mx13.intmail.prod.int.phx2.redhat.com (int-mx13.intmail.prod.int.phx2.redhat.com [10.5.11.26]) by mx1.redhat.com (Postfix) with ESMTPS id 6E2DDC0ED3E9; Fri, 22 Jan 2016 10:06:01 +0000 (UTC) Received: from sopuli.koti.laiskiainen.org (vpn1-6-136.ams2.redhat.com [10.36.6.136]) by int-mx13.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u0MA60ie023638; Fri, 22 Jan 2016 05:06:00 -0500 To: "Ananyev, Konstantin" , "Andralojc, WojciechX" References: <2601191342CEEE43887BDE71AB97725836AEC360@irsmsx105.ger.corp.intel.com> <1453364287-37283-1-git-send-email-wojciechx.andralojc@intel.com> <56A0B533.5060201@redhat.com> <2601191342CEEE43887BDE71AB97725836AEE93B@irsmsx105.ger.corp.intel.com> From: Panu Matilainen Message-ID: <56A1FF07.5060006@redhat.com> Date: Fri, 22 Jan 2016 12:05:59 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.0 MIME-Version: 1.0 In-Reply-To: <2601191342CEEE43887BDE71AB97725836AEE93B@irsmsx105.ger.corp.intel.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.68 on 10.5.11.26 Cc: "dev@dpdk.org" Subject: Re: [dpdk-dev] [PATCH v3] Patch introducing API to read/write Intel Architecture Model Specific Registers (MSR)... X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jan 2016 10:06:02 -0000 On 01/21/2016 12:51 PM, Ananyev, Konstantin wrote: > Hi Panu, > >> -----Original Message----- >> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Panu Matilainen >> Sent: Thursday, January 21, 2016 10:39 AM >> To: Andralojc, WojciechX >> Cc: dev@dpdk.org >> Subject: Re: [dpdk-dev] [PATCH v3] Patch introducing API to read/write Intel Architecture Model Specific Registers (MSR)... >> >> On 01/21/2016 10:18 AM, Wojciech Andralojc wrote: >>> Patch reworked. >>> >>> Signed-off-by: Wojciech Andralojc >>> --- >>> lib/librte_eal/common/include/arch/x86/rte_msr.h | 88 +++++++++++++++++ >>> lib/librte_eal/linuxapp/eal/Makefile | 1 + >>> lib/librte_eal/linuxapp/eal/arch/x86/rte_msr.c | 116 +++++++++++++++++++++++ >>> 3 files changed, 205 insertions(+) >>> create mode 100644 lib/librte_eal/common/include/arch/x86/rte_msr.h >>> create mode 100644 lib/librte_eal/linuxapp/eal/arch/x86/rte_msr.c >> >> This creates a new arch-specific public API, with rte_msr.h installed as >> a public header and implementation in the library (as opposed to >> inline), and so the new functions would have to be added to >> rte_eal_version.map. >> >> However that is a bit of a problem since it only exists on IA >> architectures, so it'd mean dummy entries in the version map for all >> other architectures. All the other arch-specific APIs are inline code so >> this is the first of its kind. > > My thought was: > 1. implementation is linux specific (as I know not supposed to work under freebsd). > 2. they are not supposed to be used at run-time cide-path, so no need to be inlined. Speed is not the only interesting attribute of inlining, inlined code also effectively escapes the library ABI so it does not need versioning / exporting. > 3. As I understand we plan to have a library that will use these functions anyway. Is this library going to be a generic or specific to Intel CPUs? Also, if there are no other uses for the MSR API at the moment, perhaps the best place for this code would be within that library anyway? > About dummy entries in the .map file: if we'll create a 'weak' generic implementation, > that would just return an error - would it solve the issue? Sure it'd solve the issue of dummy entries in .map but people seemed opposed to having a highly arch-specific API exposed to all architectures. - Panu -