From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id AEC8FADA4 for ; Wed, 8 Jun 2016 14:19:06 +0200 (CEST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP; 08 Jun 2016 05:18:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,438,1459839600"; d="scan'208";a="983319610" Received: from fyigit-mobl1.ger.corp.intel.com (HELO [10.237.221.53]) ([10.237.221.53]) by fmsmga001.fm.intel.com with ESMTP; 08 Jun 2016 05:18:38 -0700 To: Jerin Jacob , dev@dpdk.org References: <1464540424-12631-1-git-send-email-jerin.jacob@caviumnetworks.com> <1465317632-11471-1-git-send-email-jerin.jacob@caviumnetworks.com> <1465317632-11471-2-git-send-email-jerin.jacob@caviumnetworks.com> Cc: thomas.monjalon@6wind.com, bruce.richardson@intel.com, Maciej Czekaj , Kamil Rytarowski , Zyta Szpak , Slawomir Rosek , Radoslaw Biernacki From: Ferruh Yigit Message-ID: <57580D1E.9050800@intel.com> Date: Wed, 8 Jun 2016 13:18:38 +0100 User-Agent: Mozilla/5.0 (Windows NT 6.3; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 MIME-Version: 1.0 In-Reply-To: <1465317632-11471-2-git-send-email-jerin.jacob@caviumnetworks.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 8bit Subject: Re: [dpdk-dev] [PATCH v3 01/20] thunderx/nicvf/base: add hardware API for ThunderX nicvf inbuilt NIC X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 08 Jun 2016 12:19:07 -0000 On 6/7/2016 5:40 PM, Jerin Jacob wrote: > Adds hardware specific API for ThunderX nicvf inbuilt NIC device under > drivers/net/thunderx/nicvf/base directory. > > Signed-off-by: Jerin Jacob > Signed-off-by: Maciej Czekaj > Signed-off-by: Kamil Rytarowski > Signed-off-by: Zyta Szpak > Signed-off-by: Slawomir Rosek > Signed-off-by: Radoslaw Biernacki > --- ... > + > +struct pf_rq_cfg { union { struct { > +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ > + uint64_t reserverd1:1; doesn't really matter but, as a detail, s/reserved/reserverd ? A few more occurrence below. > + uint64_t reserverd0:34; > + uint64_t strip_pre_l2:1; > + uint64_t caching:2; > + uint64_t cq_qs:7; > + uint64_t cq_idx:3; > + uint64_t rbdr_cont_qs:7; > + uint64_t rbdr_cont_idx:1; > + uint64_t rbdr_strt_qs:7; > + uint64_t rbdr_strt_idx:1; > +#else > + uint64_t rbdr_strt_idx:1; > + uint64_t rbdr_strt_qs:7; > + uint64_t rbdr_cont_idx:1; > + uint64_t rbdr_cont_qs:7; > + uint64_t cq_idx:3; > + uint64_t cq_qs:7; > + uint64_t caching:2; > + uint64_t strip_pre_l2:1; > + uint64_t reserverd0:34; > + uint64_t reserverd1:1; > +#endif > + }; > + uint64_t value; > +}; }; > + ...