From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 35A98A04B7; Tue, 13 Oct 2020 12:30:26 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 342181D6FA; Tue, 13 Oct 2020 12:30:24 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id A0CBA1BF19 for ; Tue, 13 Oct 2020 12:30:22 +0200 (CEST) IronPort-SDR: 5sNG/qA+1B+VAwU49K3Yxs7T+IyZqbN1bDWMyCda9AN4hFqq7IqZ4qnB5ALvCOHsyre+JAdC8Z GEL0fHvaC2Yg== X-IronPort-AV: E=McAfee;i="6000,8403,9772"; a="152818303" X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="152818303" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 03:30:19 -0700 IronPort-SDR: fC7nd/eyGOKkvUc03eRASGebCy2GONbGiMmGWMb4XpTlXQVl0UKO6AGoseMJM/Tp7iuV82KNCR itc682xg7pOg== X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="530340976" Received: from fyigit-mobl1.ger.corp.intel.com (HELO [10.213.214.64]) ([10.213.214.64]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 03:30:17 -0700 To: Honnappa Nagarahalli , dev@dpdk.org, phil.yang@arm.com, thomas@monjalon.net, arybchenko@solarflare.com, Konstantin Ananyev , "jerinj@marvell.com" Cc: abhinandan.gujjar@intel.com, nd@arm.com References: <20201002000711.41511-1-honnappa.nagarahalli@arm.com> From: Ferruh Yigit Message-ID: <57cf008a-3e99-3fc7-1cc6-23455c2851e8@intel.com> Date: Tue, 13 Oct 2020 11:30:14 +0100 MIME-Version: 1.0 In-Reply-To: <20201002000711.41511-1-honnappa.nagarahalli@arm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Subject: Re: [dpdk-dev] [PATCH 1/2] lib/ethdev: replace full barrier with relaxed barrier X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 10/2/2020 1:07 AM, Honnappa Nagarahalli wrote: > From: Phil Yang > > While registering the call back functions full write barrier > can be replaced with one-way write barrier. > > Signed-off-by: Phil Yang > Signed-off-by: Honnappa Nagarahalli > Reviewed-by: Ruifeng Wang +Konstantin & Jerin, Can you please help reviewing this patch? > --- > lib/librte_ethdev/rte_ethdev.c | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/lib/librte_ethdev/rte_ethdev.c b/lib/librte_ethdev/rte_ethdev.c > index 7858ad5f1..59a41c07f 100644 > --- a/lib/librte_ethdev/rte_ethdev.c > +++ b/lib/librte_ethdev/rte_ethdev.c > @@ -26,7 +26,6 @@ > #include > #include > #include > -#include > #include > #include > #include > @@ -4527,8 +4526,12 @@ rte_eth_add_first_rx_callback(uint16_t port_id, uint16_t queue_id, > rte_spinlock_lock(&rte_eth_rx_cb_lock); > /* Add the callbacks at first position */ > cb->next = rte_eth_devices[port_id].post_rx_burst_cbs[queue_id]; > - rte_smp_wmb(); > - rte_eth_devices[port_id].post_rx_burst_cbs[queue_id] = cb; > + /* Stores to cb->fn, cb->param and cb->next should complete before > + * cb is visible to data plane threads. > + */ > + __atomic_store_n( > + &rte_eth_devices[port_id].post_rx_burst_cbs[queue_id], > + cb, __ATOMIC_RELEASE); > rte_spinlock_unlock(&rte_eth_rx_cb_lock); > > return cb; >