From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5565DA0350; Thu, 23 Dec 2021 17:06:47 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2156D40DDA; Thu, 23 Dec 2021 17:06:47 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id D5C074068C for ; Thu, 23 Dec 2021 17:06:45 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1BNDe2Xj010765 for ; Thu, 23 Dec 2021 08:06:44 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=Vg9s+PN08NhQsfm7Whgd3qJ1aVfQC+33mTpPz9IoW7k=; b=Sd7rGqd8wv9NDEQhvmZjlcQrEvDeopRyJLGz3nak426BOv44aE8jGyR8MoL2H7FVEP/7 Y/ANuTjAjT16vM5EYprEWKKLasL9mr2Qz2wJYbzAwHF5Fnc8ageCpuB8AwyFUIV98Bw1 8u2NZrs9nOJUO3FVRY3ul5VEUV3KQcyktIyvS3K5+LTmPU5Jr1EZGPYvIpaINm9P/Rq4 yAIEx+ip2uKq1seh0HW9U+3j95XUx0aTTD7ukB29Zns96K136GFxQ11PAF4AMEbMrdOV dKlsEprfUmi5F3zg2aBq9dTOvSktT7oVttxPcbEaqL7SCa1PT9iMRW2Gmo+sIoO/eTeQ 0g== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3d4t6kggg4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 23 Dec 2021 08:06:44 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 23 Dec 2021 08:06:43 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 23 Dec 2021 08:06:43 -0800 Received: from localhost.localdomain (unknown [10.28.34.29]) by maili.marvell.com (Postfix) with ESMTP id 05CAE3F708A; Thu, 23 Dec 2021 08:06:40 -0800 (PST) From: Shijith Thotton To: , Pavan Nikhilesh , "Shijith Thotton" CC: Subject: [PATCH] event/cnxk: add timer adapter periodic mode support Date: Thu, 23 Dec 2021 21:36:22 +0530 Message-ID: <5919b346b947e8a9968e974dfdede7d3ae8c0eff.1640273981.git.sthotton@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: Ca9EfBij1FdFxamOMG4BAtN_F3alzmLc X-Proofpoint-ORIG-GUID: Ca9EfBij1FdFxamOMG4BAtN_F3alzmLc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2021-12-23_03,2021-12-22_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for event timer adapter periodic mode capability. Signed-off-by: Shijith Thotton --- Depends-on: series-20928 (event/cnxk: update min interval calculation) drivers/event/cnxk/cnxk_tim_evdev.c | 21 +++++++++++++++++---- drivers/event/cnxk/cnxk_tim_evdev.h | 1 + 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c index 5d52a39752..4d22ac6ac3 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.c +++ b/drivers/event/cnxk/cnxk_tim_evdev.c @@ -58,7 +58,7 @@ cnxk_tim_chnk_pool_create(struct cnxk_tim_ring *tim_ring, } tim_ring->aura = roc_npa_aura_handle_to_aura( tim_ring->chunk_pool->pool_id); - tim_ring->ena_dfb = 0; + tim_ring->ena_dfb = tim_ring->ena_periodic ? 1 : 0; } else { tim_ring->chunk_pool = rte_mempool_create( pool_name, tim_ring->nb_chunks, tim_ring->chunk_sz, @@ -112,7 +112,9 @@ cnxk_tim_ring_info_get(const struct rte_event_timer_adapter *adptr, struct cnxk_tim_ring *tim_ring = adptr->data->adapter_priv; adptr_info->max_tmo_ns = tim_ring->max_tout; - adptr_info->min_resolution_ns = tim_ring->tck_nsec; + adptr_info->min_resolution_ns = tim_ring->ena_periodic ? + tim_ring->max_tout : + tim_ring->tck_nsec; rte_memcpy(&adptr_info->conf, &adptr->data->conf, sizeof(struct rte_event_timer_adapter_conf)); } @@ -237,6 +239,12 @@ cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr) goto tim_hw_free; } + if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_PERIODIC) { + /* Use 2 buckets to avoid contention */ + rcfg->timer_tick_ns /= 2; + tim_ring->ena_periodic = 1; + } + if (rcfg->timer_tick_ns < min_intvl_ns) { if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES) { rcfg->timer_tick_ns = min_intvl_ns; @@ -246,6 +254,9 @@ cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr) } } + if (tim_ring->ena_periodic) + rcfg->max_tmo_ns = rcfg->timer_tick_ns * 2; + if (rcfg->timer_tick_ns > rcfg->max_tmo_ns) { plt_err("Max timeout to too high"); rc = -ERANGE; @@ -322,7 +333,8 @@ cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr) if (rc < 0) goto tim_bkt_free; - rc = roc_tim_lf_config(&dev->tim, tim_ring->ring_id, clk_src, 0, 0, + rc = roc_tim_lf_config(&dev->tim, tim_ring->ring_id, clk_src, + tim_ring->ena_periodic, tim_ring->ena_dfb, tim_ring->nb_bkts, tim_ring->chunk_sz, tim_ring->tck_int, tim_ring->tck_nsec, clk_freq); if (rc < 0) { @@ -493,7 +505,8 @@ cnxk_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags, /* Store evdev pointer for later use. */ dev->event_dev = (struct rte_eventdev *)(uintptr_t)evdev; - *caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT; + *caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT | + RTE_EVENT_TIMER_ADAPTER_CAP_PERIODIC; *ops = &cnxk_tim_ops; return 0; diff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h index 6b5342cc34..91a90ee2ce 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.h +++ b/drivers/event/cnxk/cnxk_tim_evdev.h @@ -135,6 +135,7 @@ struct cnxk_tim_ring { uint8_t enable_stats; uint8_t disable_npa; uint8_t ena_dfb; + uint8_t ena_periodic; uint16_t ring_id; uint32_t aura; uint64_t nb_timers; -- 2.25.1